Marvell Semiconductor, Inc.
Design Verification Senior Principal Engineer
Marvell Semiconductor, Inc., Santa Clara, California, us, 95053
About MarvellMarvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.Your Team, Your ImpactThe Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. We develop the architecture,
IP development, SOC , create the physical design, and work with the world's leading data center and enterprise companies to bring next generation networking to reality.
What You Can ExpectLead the design verification process for complex digital designs.
Develop and execute comprehensive verification Testplans and Strategies.
Create and maintain verification environments using industry-standard tools and methodologies such as UVM/SVA and System Verilog
Collaborate with design, architecture, emulation, silicon valdiation and software teams to identify and resolve issues.
Mentor and guide junior verification engineers.
Conduct code reviews and provide feedback to ensure best practices are followed.
Analyze and debug simulation failures to identify root causes.
Analyze and close coverage, formal proofs and checklists.
Continuously improve verification processes and methodologies.
Stay up-to-date with industry trends and advancements in verification technologies.
What We're Looking ForBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
15+ years of experience in design verification, with a focus on complex digital designs.
Proficiency in verification languages such as SystemVerilog, UVM, and VHDL.
Strong understanding of digital design principles and methodologies.
Experience with industry-standard verification tools (e.g., Cadence, Synopsys, Mentor Graphics).
Excellent problem-solving and debugging skills.
Strong leadership and mentoring abilities.
Effective communication and collaboration skills.
Ability to work in a fast-paced, dynamic environment.
Preferred Qualifications:Experience with formal verification techniques.
Understanding of Ethernet networking
Experience with Emulation.
Knowledge of scripting languages (e.g., Python, Perl).
Familiarity with FPGA and ASIC design flows.
Experience in low-power design verification.
Expected Base Pay Range (USD)160,200 - 240,000, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
The expected base pay range for this role may be modified based on market conditions.Additional Compensation and Benefit ElementsAt Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
TAOps@marvell.com.#LI-MM1#J-18808-Ljbffr
IP development, SOC , create the physical design, and work with the world's leading data center and enterprise companies to bring next generation networking to reality.
What You Can ExpectLead the design verification process for complex digital designs.
Develop and execute comprehensive verification Testplans and Strategies.
Create and maintain verification environments using industry-standard tools and methodologies such as UVM/SVA and System Verilog
Collaborate with design, architecture, emulation, silicon valdiation and software teams to identify and resolve issues.
Mentor and guide junior verification engineers.
Conduct code reviews and provide feedback to ensure best practices are followed.
Analyze and debug simulation failures to identify root causes.
Analyze and close coverage, formal proofs and checklists.
Continuously improve verification processes and methodologies.
Stay up-to-date with industry trends and advancements in verification technologies.
What We're Looking ForBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
15+ years of experience in design verification, with a focus on complex digital designs.
Proficiency in verification languages such as SystemVerilog, UVM, and VHDL.
Strong understanding of digital design principles and methodologies.
Experience with industry-standard verification tools (e.g., Cadence, Synopsys, Mentor Graphics).
Excellent problem-solving and debugging skills.
Strong leadership and mentoring abilities.
Effective communication and collaboration skills.
Ability to work in a fast-paced, dynamic environment.
Preferred Qualifications:Experience with formal verification techniques.
Understanding of Ethernet networking
Experience with Emulation.
Knowledge of scripting languages (e.g., Python, Perl).
Familiarity with FPGA and ASIC design flows.
Experience in low-power design verification.
Expected Base Pay Range (USD)160,200 - 240,000, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
The expected base pay range for this role may be modified based on market conditions.Additional Compensation and Benefit ElementsAt Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
TAOps@marvell.com.#LI-MM1#J-18808-Ljbffr