Timing Methodology Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.THE ROLE:In this senior position, you will be defining, developing, and driving timing methodologies across the Adaptive and Embedded Computing Group. You will work closely with architecture, product planning, process, design, and product engineering teams to realize silicon solutions with best-in-class PPA (performance power area). You will bring your experience and expertise to solve the teams most pressing challenges in sign-off and modeling methodologies at 2nm and beyond on monolithic and 2.5/3DIC adaptive SOCs and FPGAs. Your solutions will enable products to compete in markets from the edge to the cloud while pushing the limits of performance and efficiency.THE PERSON:You are detailed oriented, possessing effective communication skills, and an experienced problem solver. You are passionate about optimizing for power, performance and area while meeting schedules and managing cost. You embrace cross-functional collaboration and continuous learning. You are comfortable in converting high level requirements from product planning, foundry, and other stakeholders into a set of methodologies and guidelines for the design community.KEY RESPONSIBILITIES:Define, develop, and drive design, timing, and power methodologies for advance process nodes.Collaborate with implementation and sign-off teams.Collaborate with CAD, power integrity, foundry teams and EDA vendors to understand margins and sign-off risks and develop mitigation strategies.PREFERRED EXPERIENCE:Experienced custom, physical design and/or sign-off engineer.Expert user of industry-standard physical design, analysis, and sign-off tools.Experience with FPGA implementation tools.Experience advocating for technical solutions in a collaborative team environment.Good programming skills (Python, Perl, Tcl).ACADEMIC CREDENTIALS:Bachelor's or above in Electrical Engineering, Computer Engineering etc.LOCATION:San Jose, CA

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