Cadence Design Systems
AE Senior Manager – Serdes Applications
Cadence Design Systems, San Jose, California, United States, 95199
AE Senior Manager – Serdes ApplicationsLocation:
San Jose, CA
Job Description:
Cadence is seeking a motivated, detail-oriented, and creative individual to join the Worldwide IP Sales team as Sr. Applications Engineering Manager for our Serdes IP Portfolio. The ideal candidate for this position is a seasoned High-Speed Interface Technologist who enjoys leading a team of skilled engineers and working with customers to develop solutions for their System/ASIC/SoC designs using the Cadence Serdes IP portfolio. This is a pre-sales role, perfect for someone who has System/ASIC/SoC design experience and great interpersonal and communication skills, committed to the success of our customers. You will have an opportunity to work across various market segments (AI, Cloud, Networking, Storage…), designs, foundries, and leading/bleeding edge processes and build credibility in solving the toughest high-speed interface challenges.
Responsibilities include:
Leading a high performing team of application engineers to the next level of success.
Developing appropriate strategies to win deals.
Collaborating with the sales & marketing teams to identify and understand the technical and business challenges of our customers.
Developing solutions for customers, leveraging the broad Cadence IP portfolio.
Educating our customers on how the IP products meet their needs and helping them evaluate the IP (with support from the product R&D teams) relative to their requirements.
Influencing the IP product development roadmap by communicating customer needs to the product R&D teams.
Keeping up with industry trends and protocol evolutions at PCI-SIG and other standards bodies.
Managing and supporting the engagements via on-site or remote technical interactions, providing demos, supporting evaluations, resolving technical problems, addressing competitive challenges and regularly communicating status among cross-functional teams.
Qualifications and Experience:
MSEE with 15+ years of relevant experience, or PhD with 10+ years of relevant experience.
Management experience leading a highly technical team.
Understanding of latest SoC architectures and system-level design practices for market segments (mobile, storage, automotive, networking, IoT) particularly from IP requirements perspective.
Prior experience and knowledge of one or more interface and connectivity protocols, e.g. PCIe, CXL, UCIe, Ethernet, USB, MIPI, 112G, 56G.
Familiarity with state-of-the-art SoC design implementation: RTL design, synthesis and static timing analysis, physical design flow, testbench creation and simulation, some familiarity with analog/mixed-signal design and verification flows, and basic understanding of foundry, package and PCB design flows and technologies.
Prior experience in selecting, using, designing or supporting PHY and/or controller interface IP, internal or external.
Ability to understand and present complex technical requirements, problems, and solutions concisely in verbal and written communications.
Ability to organize, conduct and coordinate meetings involving multiple teams, internal and external.
Travel (~10%) may be required to visit customers, sales, and engineering locations.
The annual salary range for California is $138,600 to $257,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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San Jose, CA
Job Description:
Cadence is seeking a motivated, detail-oriented, and creative individual to join the Worldwide IP Sales team as Sr. Applications Engineering Manager for our Serdes IP Portfolio. The ideal candidate for this position is a seasoned High-Speed Interface Technologist who enjoys leading a team of skilled engineers and working with customers to develop solutions for their System/ASIC/SoC designs using the Cadence Serdes IP portfolio. This is a pre-sales role, perfect for someone who has System/ASIC/SoC design experience and great interpersonal and communication skills, committed to the success of our customers. You will have an opportunity to work across various market segments (AI, Cloud, Networking, Storage…), designs, foundries, and leading/bleeding edge processes and build credibility in solving the toughest high-speed interface challenges.
Responsibilities include:
Leading a high performing team of application engineers to the next level of success.
Developing appropriate strategies to win deals.
Collaborating with the sales & marketing teams to identify and understand the technical and business challenges of our customers.
Developing solutions for customers, leveraging the broad Cadence IP portfolio.
Educating our customers on how the IP products meet their needs and helping them evaluate the IP (with support from the product R&D teams) relative to their requirements.
Influencing the IP product development roadmap by communicating customer needs to the product R&D teams.
Keeping up with industry trends and protocol evolutions at PCI-SIG and other standards bodies.
Managing and supporting the engagements via on-site or remote technical interactions, providing demos, supporting evaluations, resolving technical problems, addressing competitive challenges and regularly communicating status among cross-functional teams.
Qualifications and Experience:
MSEE with 15+ years of relevant experience, or PhD with 10+ years of relevant experience.
Management experience leading a highly technical team.
Understanding of latest SoC architectures and system-level design practices for market segments (mobile, storage, automotive, networking, IoT) particularly from IP requirements perspective.
Prior experience and knowledge of one or more interface and connectivity protocols, e.g. PCIe, CXL, UCIe, Ethernet, USB, MIPI, 112G, 56G.
Familiarity with state-of-the-art SoC design implementation: RTL design, synthesis and static timing analysis, physical design flow, testbench creation and simulation, some familiarity with analog/mixed-signal design and verification flows, and basic understanding of foundry, package and PCB design flows and technologies.
Prior experience in selecting, using, designing or supporting PHY and/or controller interface IP, internal or external.
Ability to understand and present complex technical requirements, problems, and solutions concisely in verbal and written communications.
Ability to organize, conduct and coordinate meetings involving multiple teams, internal and external.
Travel (~10%) may be required to visit customers, sales, and engineering locations.
The annual salary range for California is $138,600 to $257,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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