LeadStack
Design Verification Engineer
LeadStack, San Jose, California, United States, 95199
LeadStack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world.
Title:
Design Verification EngineerLocation:
San Jose CA - HybridDuration:
12 Months
Job Description:As a Design Verification Engineer, you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.
Note:Current state-of-the-art testbench development such as UVM methodologyExperience in design verification with UVM and SystemVerilog is a MUST
Responsibilities:Triage regression failures and make testbench updatesDebug functional errors in RTL model using simulation and debug tools.Maintain efficient and clean regression statusDevelop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.Review Architecture and Micro-Architecture specifications.Closely work with Architects and RTL designers.Define, maintain and execute unit level and/or Cluster level verification testplans.Generate and run Testcases on logic simulation models.Code Functional coverage models and System Verilog assertions.Drive Functional Coverage and Code coverage to closure.Integrate C++ reference model into Scoreboards
Requirements:5-15 year's industry experience in a design verification role.Proficient in System Verilog/UVM/OVM, OOP/C++Knowledge of GPU, experience with Shader, Texture, or Memory System a plusExperience with code coverage and functional coverage driven verification methodology.Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench.Excellent working knowledge of scripting languages such as Python or Perl.Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines.Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.Strong debugging skillsStrong programming skills with good understanding of algorithms and data structuresGood verbal and written communication skills.
If interested, please share your updated resume and the best time and number to connect over the phone. In case you are not available/interested, will appreciate if you can share it with your friends/network. Your referrals are appreciated!
To know more about current opportunities at LeadStack, please visit us at
https://leadstackinc.com/careers/Should you have any questions, feel free to call me on 415 985-0816 or send an email to
Nishanth.allam@leadstackinc.com
#J-18808-Ljbffr
Title:
Design Verification EngineerLocation:
San Jose CA - HybridDuration:
12 Months
Job Description:As a Design Verification Engineer, you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.
Note:Current state-of-the-art testbench development such as UVM methodologyExperience in design verification with UVM and SystemVerilog is a MUST
Responsibilities:Triage regression failures and make testbench updatesDebug functional errors in RTL model using simulation and debug tools.Maintain efficient and clean regression statusDevelop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.Review Architecture and Micro-Architecture specifications.Closely work with Architects and RTL designers.Define, maintain and execute unit level and/or Cluster level verification testplans.Generate and run Testcases on logic simulation models.Code Functional coverage models and System Verilog assertions.Drive Functional Coverage and Code coverage to closure.Integrate C++ reference model into Scoreboards
Requirements:5-15 year's industry experience in a design verification role.Proficient in System Verilog/UVM/OVM, OOP/C++Knowledge of GPU, experience with Shader, Texture, or Memory System a plusExperience with code coverage and functional coverage driven verification methodology.Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench.Excellent working knowledge of scripting languages such as Python or Perl.Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines.Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.Strong debugging skillsStrong programming skills with good understanding of algorithms and data structuresGood verbal and written communication skills.
If interested, please share your updated resume and the best time and number to connect over the phone. In case you are not available/interested, will appreciate if you can share it with your friends/network. Your referrals are appreciated!
To know more about current opportunities at LeadStack, please visit us at
https://leadstackinc.com/careers/Should you have any questions, feel free to call me on 415 985-0816 or send an email to
Nishanth.allam@leadstackinc.com
#J-18808-Ljbffr