Marvell Semiconductor, Inc.
Principal Design Verification Engineer
Marvell Semiconductor, Inc., Santa Clara, California, us, 95053
About MarvellMarvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.Your Team, Your ImpactThe Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. We develop the architecture, collaborate on IP development, create the physical design, and work with the world's leading data center and enterprise companies to bring next generation networking to reality
What You Can ExpectVerifying block or sub-block of complex SoCs through simulation of register-transfer level (RTL) and gate level designs using industry standard tools and processes
Develop constrained-random verification test environment using System Verilog, UVM and C programming, including testbenches, checkers, monitors, drivers and other testbench components.
Collaborate closely with design and other verification engineers to develop and implement verification test plans, schedules, and project deliverables.
Manage, debug tests and regression failures.
Maintain and improves existing functional verification infrastructure and methodology.
What We're Looking ForBS or MS in Computer or Electrical Engineering
10 to 15 years hands-on experience with focus on front-end complex RTL verification
Experience with constrained-random verification test environments using System Verilog and UVM
Highly motivated and skillful at solving difficult technical problems.
Experience with scripting in Perl/Python/Shell
Networking, Storage and/or SOC experience is a plus.
#LI-MM1Expected Base Pay Range (USD)137,510 - 206,000, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
The expected base pay range for this role may be modified based on market conditions.Additional Compensation and Benefit ElementsAt Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
TAOps@marvell.com.
#J-18808-Ljbffr
What You Can ExpectVerifying block or sub-block of complex SoCs through simulation of register-transfer level (RTL) and gate level designs using industry standard tools and processes
Develop constrained-random verification test environment using System Verilog, UVM and C programming, including testbenches, checkers, monitors, drivers and other testbench components.
Collaborate closely with design and other verification engineers to develop and implement verification test plans, schedules, and project deliverables.
Manage, debug tests and regression failures.
Maintain and improves existing functional verification infrastructure and methodology.
What We're Looking ForBS or MS in Computer or Electrical Engineering
10 to 15 years hands-on experience with focus on front-end complex RTL verification
Experience with constrained-random verification test environments using System Verilog and UVM
Highly motivated and skillful at solving difficult technical problems.
Experience with scripting in Perl/Python/Shell
Networking, Storage and/or SOC experience is a plus.
#LI-MM1Expected Base Pay Range (USD)137,510 - 206,000, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
The expected base pay range for this role may be modified based on market conditions.Additional Compensation and Benefit ElementsAt Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
TAOps@marvell.com.
#J-18808-Ljbffr