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Go to next pageSynapse Design Inc. - Santa Clara, CA, US, 95053
Work at Synapse Design Inc.
Direct message the job poster from Synapse Design Inc.
Talent Acquisition Lead @ Synapse || Ex-Qualcomm || Ex-NVIDIA || VLSI/Semiconductor Recruitment Professional
Physical Design Engineer
Job Responsibilities:
- Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors.
- Drive frontend and backend implementation from RTL to gds2, including synthesis, FV, floorplanning, netlisting, timing constraints, timing and power convergence, and ECO implementation.
- Responsible for hands-on physical implementation and timing closure of core platforms and SoCs.
- Work with Systems and Application team to drive timing closure friendly SoC architecture and IO interfaces/IO pin.
- Streamline the timing signoff criteria, timing analysis methodologies and flows (critical path spice simulation) and develop/enhance auto ECO generation scripts for timing closure.
- Responsible for floor planning, physical synthesis, and physical design closure of large complex designs at 1GHz+ clock cycles.
- Synthesis engineer for a low-power SoC.
- Drive physical design and timing convergence of high-frequency low-power CPU, GPU, and/or ASIC at block level, cluster level, and/or full chip level.
- Clock distribution and CTS for 1 GHz+ designs.
Seniority level
Mid-Senior level
Employment type
Full-time
Job function
Semiconductors
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Physical Design Engineer
