Tech Providers, Inc.
Contract Hardware Engineer Mid. Job at Tech Providers, Inc. in Ce...
Tech Providers, Inc. - Cedar Rapids, IA, United States, 52498
Work at Tech Providers, Inc.
Overview
- View job
Overview
Description Requisition Status: Pending Status Reason: Pending Sourcing Reason: Vacant Position Reason Detail: Manager: Department: Cost of goods sold : 1100 Job Category: IT Job Code: 7252:Contract Hardware Engineer Mid. Job Title: Contract Hardware Engineer Mid. Keywords: Number of Positions: 1 Remaining Positions: 1 Duties:
NOTE: Due to nature of the project, U.S. Citizenship is must for this role ,please do mention on top of resume if candidate have Active security clearance or not.
CW will work onsite from day one at Cedar Rapids, IA (5 days onsite)
Experience range - 6-15 years
•Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration
•Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
•Contribute to engineering estimates for new program pursuits.
•May provide technical leadership for project design teams by breaking down work, planning activities, and reporting status
Must have Skills:
•RTL coding and simulation in VHDL/Veriog
•Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
•Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
•Git, Subversion
•Experience with Unix, scripting, C/C++, and/or Perl
Preferred Skills:
•Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
•SIC / FPGA lab validation with advanced lab equipment
•Design for Test (DFT) and manufacturability issues
•Experience with Unix, scripting, C/C++, and/or Perl
Any special or skills related notes:
bility to work with minimal supervision, team with engineers of a variety of skills and backgrounds, and matrix into projects with aggressive schedules and frequent milestones
Strong oral and written communication skills with the ability to document and present one's work and status
Skills:
NOTE: Due to nature of the project, U.S. Citizenship is must for this role ,please do mention on top of resume if candidate have Active security clearance or not.
CW will work onsite from day one at Cedar Rapids, IA (5 days onsite)
Experience range - 6-15 years
•Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration
•Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
•Contribute to engineering estimates for new program pursuits.
•May provide technical leadership for project design teams by breaking down work, planning activities, and reporting status
Must have Skills:
•RTL coding and simulation in VHDL/Veriog
•Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
•Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
•Git, Subversion
•Experience with Unix, scripting, C/C++, and/or Perl
Preferred Skills:
•Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
•SIC / FPGA lab validation with advanced lab equipment
•Design for Test (DFT) and manufacturability issues
•Experience with Unix, scripting, C/C++, and/or Perl
Any special or skills related notes:
bility to work with minimal supervision, team with engineers of a variety of skills and backgrounds, and matrix into projects with aggressive schedules and frequent milestones
Strong oral and written communication skills with the ability to document and present one's work and status
Education:
Bachelor's of engineering
ttachments:
Location Client Location Country: United States State/Province: Iow City: Cedar Rapids ddress: 400 Collins Rd NE, US0426 POSTAL CODE: 52498 Work Location Same as Client Location Other Client Location Work Completed Offsite Schedule Start Date: 05/19/2025 Hours Per Week: 40.00 Est. End Date: 05/08/2026 Hours Per Day: 8.00 Schedule Notes: Days Per Week: 5.00 Financials Department: Cost of goods sold : 1100 Max Rate: $100.00 Rate Application: Per Hour Currency: USD Supplier FLSA Classification: N/ Sub-Contracted Worker: No Contact Information MSP Contact: Srivastava, Abhishek dditional Contact: MSP Phone: dditional Phone: HR Contact: dditional Email: Operations Specialist Contact: Operations Specialist Phone : Supplier Notes Contacts Requisition Custom Fields Dates of Interest Date Created: 04/28/2025 Date Closed: Date Pending: 04/28/2025 Date Cancelled:
NOTE: Due to nature of the project, U.S. Citizenship is must for this role ,please do mention on top of resume if candidate have Active security clearance or not.
CW will work onsite from day one at Cedar Rapids, IA (5 days onsite)
Experience range - 6-15 years
•Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration
•Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
•Contribute to engineering estimates for new program pursuits.
•May provide technical leadership for project design teams by breaking down work, planning activities, and reporting status
Must have Skills:
•RTL coding and simulation in VHDL/Veriog
•Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
•Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
•Git, Subversion
•Experience with Unix, scripting, C/C++, and/or Perl
Preferred Skills:
•Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
•SIC / FPGA lab validation with advanced lab equipment
•Design for Test (DFT) and manufacturability issues
•Experience with Unix, scripting, C/C++, and/or Perl
Any special or skills related notes:
bility to work with minimal supervision, team with engineers of a variety of skills and backgrounds, and matrix into projects with aggressive schedules and frequent milestones
Strong oral and written communication skills with the ability to document and present one's work and status
Skills:
NOTE: Due to nature of the project, U.S. Citizenship is must for this role ,please do mention on top of resume if candidate have Active security clearance or not.
CW will work onsite from day one at Cedar Rapids, IA (5 days onsite)
Experience range - 6-15 years
•Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration
•Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
•Contribute to engineering estimates for new program pursuits.
•May provide technical leadership for project design teams by breaking down work, planning activities, and reporting status
Must have Skills:
•RTL coding and simulation in VHDL/Veriog
•Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
•Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
•Git, Subversion
•Experience with Unix, scripting, C/C++, and/or Perl
Preferred Skills:
•Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
•SIC / FPGA lab validation with advanced lab equipment
•Design for Test (DFT) and manufacturability issues
•Experience with Unix, scripting, C/C++, and/or Perl
Any special or skills related notes:
bility to work with minimal supervision, team with engineers of a variety of skills and backgrounds, and matrix into projects with aggressive schedules and frequent milestones
Strong oral and written communication skills with the ability to document and present one's work and status
Education:
Bachelor's of engineering
ttachments:
Location Client Location Country: United States State/Province: Iow City: Cedar Rapids ddress: 400 Collins Rd NE, US0426 POSTAL CODE: 52498 Work Location Same as Client Location Other Client Location Work Completed Offsite Schedule Start Date: 05/19/2025 Hours Per Week: 40.00 Est. End Date: 05/08/2026 Hours Per Day: 8.00 Schedule Notes: Days Per Week: 5.00 Financials Department: Cost of goods sold : 1100 Max Rate: $100.00 Rate Application: Per Hour Currency: USD Supplier FLSA Classification: N/ Sub-Contracted Worker: No Contact Information MSP Contact: Srivastava, Abhishek dditional Contact: MSP Phone: dditional Phone: HR Contact: dditional Email: Operations Specialist Contact: Operations Specialist Phone : Supplier Notes Contacts Requisition Custom Fields Dates of Interest Date Created: 04/28/2025 Date Closed: Date Pending: 04/28/2025 Date Cancelled: