Cadence
Principal FPGA Design Engineer
Cadence - San Jose, California, United States, 95199
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Principal FPGA Design Engineer
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Cadence 2 days ago Be among the first 25 applicants Join to apply for the
Principal FPGA Design Engineer
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Cadence At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Protium Prototyping Platform is part of the Cadence Dynamic Duo that has been a huge success with our customers. With CadenceProtium prototyping platforms, design and verification teams can rapidly bring up a prototype and provide a pre-silicon platform for early software development, system validation, and hardware regressions.
Protium is leading product in FPGA Emulation/Prototyping domain. This role is to design, verification, timing closure and hardware validation of the FPGA IPs.
Developing field-programmable gate array intellectual properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware; Enhancing current IPs as well as developing new IPs. Debug and fix internal regression failures for FPGA IPs. Documentation of IPs
The ideal candidate will have the following skills and experience:
Master degree in Electrical Engineering with 5+ years of experience Experience with FPGA design and verification using Verilog Experience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation, Place and route Experience in debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/software Experience using Linux servers, Script development using Shell/Perl/TCL Experience using Cadence Simulators Incisive or Xcelium Detailed knowledge about industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI
The annual salary range for California is $131,600 to $244,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Software Development Referrals increase your chances of interviewing at Cadence by 2x Get notified about new Principal Design Engineer jobs in
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Principal FPGA Design Engineer
role at
Cadence 2 days ago Be among the first 25 applicants Join to apply for the
Principal FPGA Design Engineer
role at
Cadence At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Protium Prototyping Platform is part of the Cadence Dynamic Duo that has been a huge success with our customers. With CadenceProtium prototyping platforms, design and verification teams can rapidly bring up a prototype and provide a pre-silicon platform for early software development, system validation, and hardware regressions.
Protium is leading product in FPGA Emulation/Prototyping domain. This role is to design, verification, timing closure and hardware validation of the FPGA IPs.
Developing field-programmable gate array intellectual properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware; Enhancing current IPs as well as developing new IPs. Debug and fix internal regression failures for FPGA IPs. Documentation of IPs
The ideal candidate will have the following skills and experience:
Master degree in Electrical Engineering with 5+ years of experience Experience with FPGA design and verification using Verilog Experience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation, Place and route Experience in debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/software Experience using Linux servers, Script development using Shell/Perl/TCL Experience using Cadence Simulators Incisive or Xcelium Detailed knowledge about industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI
The annual salary range for California is $131,600 to $244,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Software Development Referrals increase your chances of interviewing at Cadence by 2x Get notified about new Principal Design Engineer jobs in
San Jose, CA . Senior Research And Development Engineer
Senior Design and Simulation Engineer (HIL)
Senior Mechanical Engineer – Interconnect Design
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Tech Lead Mechanical Engineer (Principal level)
Union City, CA $120,000.00-$188,000.00 1 week ago Santa Clara, CA $128,000.00-$247,250.00 2 hours ago Senior Mechanical Engineer - Cylinder Design
Menlo Park, CA $126,000.00-$148,000.00 2 weeks ago Principal Software Engineer - Data Platform
Senior Thermal Solutions Design Engineer
Fremont, CA $136,238.00-$188,512.00 1 week ago Senior Mechanical Engineer, Stapling Design
Staff Mechanical Engineer - Cylinder Design
Menlo Park, CA $148,000.00-$169,999.00 2 weeks ago Sr. Principal Engineer, Hardware Design (AI2411)
San Jose, CA $240,000.00-$317,200.00 1 day ago San Jose, CA $150,000.00-$230,000.00 6 hours ago Principal High-Speed Photonics Design Engineer
Santa Clara County, CA $171,000.00-$257,000.00 15 hours ago San Jose, CA $153,600.00-$286,600.00 2 weeks ago Fremont, CA $129,900.00-$160,000.00 1 day ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr