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The application window is expected to close on 6/30/2025

This is an onsite role with a strong preference working out of the Maynard, MA office location, but can also be based out of our San Jose, CA or RTP, NC offices.

Meet the Team:

Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world's best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.

Your Impact:

As part of a growing Design Verification Team, you will work with other verification, DSP, and RTL engineers to ensure successful verification of complex ASICs throughout its pre-silicon lifecycle. You will work with C++ and UVM building test-benches and gathering and analyzing coverage reports. Responsibilities include:

• Develop detailed and comprehensive test plans.
• Develop verification test benches at block, inter-block, and chip levels.
• Apply innovative verification techniques to complex designs.
• Participate in the review of design verification coding and coverage metrics.
• Work collaboratively with the team to develop & incorporate the latest test technologies & processes.

Minimum Qualifications:

• Bachelor's degree and 5+ years of experience, or a Master's degree and 3+ years majoring in Computer Science, Computer Engineering, or Electronic/Electrical Engineering.
• Demonstrated experience in ASIC design verification methodologies and flows.
• Experience with C++ model co-simulation.
• Experience with HVL and HDL languages and tools, scripting and programming languages Verilog, System Verilog, C++, Perl and/or Python.

• UVM experience is a plus
• Strong problem solving, communication, and team skills.
• Experience in object oriented programming.
• Networking knowledge is preferred, but not essential.

Why Cisco?

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.