CyberCoders
Principal ASIC Design Verification Engineer - UVM, PCIe, CXL
CyberCoders, San Jose, California, United States, 95199
Principal ASIC Design Verification Engineer - UVM, PCIe, CXL
Job Location:
San Jose, CACompensation:
$180K - $240K base Depending on experience plus stock options!Requirements:
ASIC Design, Verification, UVM, PCIe, CXLWe were founded in 2020 by a team of veterans in Silicon Valley, and our mission is to accelerate AI computing in data centers and HPC by introducing high-performance, power efficient, scalable and cost-effective interconnect solutions. AI computing and data center architectures are undergoing a fundamental transformation of disaggregation and composability, driven by the enablement of CXL (Computing Express Link) technology.We are working on a CXL/PCIe-based chip for cloud computing applications. We're expanding our team and looking to add a Principal ASIC Design Verification Engineer.Top Reasons to Work with Us
Competitive Compensation ($180K - $240K base Depending on Experience)Comprehensive Benefits package including stock options!The chance to join a small start-up tackling challenging problems with huge upside potential!What You Will Be Doing
Test bench development using System Verilog UVMTest plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collectionsRegression setup and debug at RTL level and gate sim level working with the design teamWhat You Need for this Position
Must have a Bachelor's (Master's or Ph.D. preferred) in Computer Science, Electrical Engineering, Computer Engineering, or similar with 10+ years of experience:Design Verification experienceDeep knowledge of System Verilog, UVM, and verification coverage matrixFamiliar with Synopsys PCIe/CXL VIP and Mentor Graphics QVIPStrong experience with PCIe/CXL protocol (PHY/DLLP/TLP)Very familiar with the peripheral protocols such as UART, I2C, SPI FlashProficient in Perl scriptingSo, if you are a Principal ASIC Design Verification Engineer with UVM and PCIe and/or CXL experience, please apply today! or send an updated copy of your resume to
Mike.Vandenbergh@CyberCoders.com
for immediate consideration!Applicants must be authorized to work in the U.S.CyberCoders, Inc is proud to be an Equal Opportunity EmployerAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.
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Job Location:
San Jose, CACompensation:
$180K - $240K base Depending on experience plus stock options!Requirements:
ASIC Design, Verification, UVM, PCIe, CXLWe were founded in 2020 by a team of veterans in Silicon Valley, and our mission is to accelerate AI computing in data centers and HPC by introducing high-performance, power efficient, scalable and cost-effective interconnect solutions. AI computing and data center architectures are undergoing a fundamental transformation of disaggregation and composability, driven by the enablement of CXL (Computing Express Link) technology.We are working on a CXL/PCIe-based chip for cloud computing applications. We're expanding our team and looking to add a Principal ASIC Design Verification Engineer.Top Reasons to Work with Us
Competitive Compensation ($180K - $240K base Depending on Experience)Comprehensive Benefits package including stock options!The chance to join a small start-up tackling challenging problems with huge upside potential!What You Will Be Doing
Test bench development using System Verilog UVMTest plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collectionsRegression setup and debug at RTL level and gate sim level working with the design teamWhat You Need for this Position
Must have a Bachelor's (Master's or Ph.D. preferred) in Computer Science, Electrical Engineering, Computer Engineering, or similar with 10+ years of experience:Design Verification experienceDeep knowledge of System Verilog, UVM, and verification coverage matrixFamiliar with Synopsys PCIe/CXL VIP and Mentor Graphics QVIPStrong experience with PCIe/CXL protocol (PHY/DLLP/TLP)Very familiar with the peripheral protocols such as UART, I2C, SPI FlashProficient in Perl scriptingSo, if you are a Principal ASIC Design Verification Engineer with UVM and PCIe and/or CXL experience, please apply today! or send an updated copy of your resume to
Mike.Vandenbergh@CyberCoders.com
for immediate consideration!Applicants must be authorized to work in the U.S.CyberCoders, Inc is proud to be an Equal Opportunity EmployerAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.
#J-18808-Ljbffr