Rambus, Inc.
Dir Digital Engineering
Rambus, Inc., Atlanta, Georgia, United States, 30383
The candidate will be part of Rambus Memory Interface Chips BU’s design group responsible for specifying, architecting, executing and productizing leading edge memory interface buffer chips for DDR5, DDR6 and beyond.ResponsibilitiesLead and manage a team of digital design engineers at various levels
Main tasks include overall project planning and execution, schedule risk and priority management, providing technical direction and guidance, fostering innovation, performance reviews, team talent development
Work closely with cross-functional teams across different geographies and time zones to ensure engagement and execution
Hands-on front-end design including architecture definition, RTL design, Verilog simulation, synthesis, timing closure, GLS, HSPICE correlation and DFT
Work closely with design verification team
Other responsibilities include design documentation, customer interaction and post silicon activity support
QualificationsMSEE/Ph.D. with 10+ years of digital/RTL design experience
Direct chip design experience in DDR product is a strong plus
Experience with memory buffers (RCD and DB) is a strong plus
Familiarity with UVM based design verification is a strong plus
Must be a team player with good written and verbal communication skills, self-motivated, thorough design styles, detail oriented, and work with multiple functional teams with good engineering practices.
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Main tasks include overall project planning and execution, schedule risk and priority management, providing technical direction and guidance, fostering innovation, performance reviews, team talent development
Work closely with cross-functional teams across different geographies and time zones to ensure engagement and execution
Hands-on front-end design including architecture definition, RTL design, Verilog simulation, synthesis, timing closure, GLS, HSPICE correlation and DFT
Work closely with design verification team
Other responsibilities include design documentation, customer interaction and post silicon activity support
QualificationsMSEE/Ph.D. with 10+ years of digital/RTL design experience
Direct chip design experience in DDR product is a strong plus
Experience with memory buffers (RCD and DB) is a strong plus
Familiarity with UVM based design verification is a strong plus
Must be a team player with good written and verbal communication skills, self-motivated, thorough design styles, detail oriented, and work with multiple functional teams with good engineering practices.
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