Synopsys, Inc.
ASIC Digital Design, Sr Staff Engineer
Synopsys, Inc., Sunnyvale, California, United States, 94087
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and get differentiated products to market quickly with reduced risk.DDR IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of DDR IP products. All current and next-generation technologies are being developed by the DDR IP team. Both digital and analog components complement each other in creating a high-performance, high-bandwidth, low-latency, and low-power product. In this role, you will be responsible for developing test benches and verifying integrated IP Subsystems for our global customers.Responsibilities:
Defining and tracking Verification test plansDesigning and writing constrained-random SystemVerilog testbenches using a UVMWriting SystemVerilog assertionsWriting functional coverageDebugging RTL and GLS failuresCode coverage AnalysisProviding mentoring and guidance to less experienced team membersRequired Skills:
BSEE in EE with 8+ years of industry experienceDigital verification in UVM environment; Formal Verification is a plusUnderstanding of DDR memory and DDRPHY architectureKnowledge of DFI, Memory Controller or Memory SubsystemVerilog, System Verilog and Perl/Python scripting skillsDebugging skillsDemonstrates good communication and problem-solving skillsUnderstanding of high-speed interface protocols is a plusAt Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.The base salary range across the U.S. for this role is between $156,000-$233,000. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education.
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Defining and tracking Verification test plansDesigning and writing constrained-random SystemVerilog testbenches using a UVMWriting SystemVerilog assertionsWriting functional coverageDebugging RTL and GLS failuresCode coverage AnalysisProviding mentoring and guidance to less experienced team membersRequired Skills:
BSEE in EE with 8+ years of industry experienceDigital verification in UVM environment; Formal Verification is a plusUnderstanding of DDR memory and DDRPHY architectureKnowledge of DFI, Memory Controller or Memory SubsystemVerilog, System Verilog and Perl/Python scripting skillsDebugging skillsDemonstrates good communication and problem-solving skillsUnderstanding of high-speed interface protocols is a plusAt Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.The base salary range across the U.S. for this role is between $156,000-$233,000. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education.
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