Chelsea Search Group, Inc.
Senior Timing (STA) Engineer
Chelsea Search Group, Inc., Austin, Texas, us, 78716
Senior STA Engineer
Austin, Texas (onsite/hybrid)
US Citizen or US Permanent Resident
6-12 months contract with possible extensions
Role & Responsibilities:
• Top/Block Level Constraints Development: Design and develop constraints at the top and block levels to ensure robust performance and functionality of the design.
• CDC & Lint Checks: Perform Clock Domain Crossing (CDC) and Lint checks to ensure the reliability and accuracy of the design.
• STA Timing Closure: Conduct Static Timing Analysis (STA) to achieve timing closure and meet design specifications.
• SDC Quality Control (QC): Perform quality control on Synopsys Design Constraints (SDC) files to ensure their correctness and efficiency.
• Scripting: Develop and maintain scripts using TCL, Perl, and Python to automate various aspects of the design process.
• Tool Knowledge: Utilize tools such as PrimeTime, Tweaker, and other industry-standard software for design and analysis.
• SDC Writing: Write and optimize SDC files to define timing constraints and guide the design process.
Skills Required:
• STA (Static Timing Analysis):
- Develop constraints from scratch for top-level designs.
- Possess strong timing concepts and the ability to apply them effectively.
- Have a good understanding of tools such as StarRC/PrimeTime or QRC/Tempus.
- Ability to interpret timing reports, analyze and identify timing bottlenecks.
- Exposure to the timing closure flow and methodologies.
• Tools Expertise:
- Proficient in PrimeTime, Spyglass, Tempus, QRC, and STAR-RC.
• Scripting Proficiency:
- Skilled in scripting languages such as TCL, Perl, and Python for automating design processes and enhancing efficiency.
Qualifications:
• BSEE required, MSEE preferred
• Proven experience in STA, SDC writing, and timing closure.
• Strong analytical skills and attention to detail.
• Ability to work independently and as part of a team.
• Excellent problem-solving skills and the ability to troubleshoot complex design issues.
#STA #StaticTimingAnalysis#J-18808-Ljbffr
Austin, Texas (onsite/hybrid)
US Citizen or US Permanent Resident
6-12 months contract with possible extensions
Role & Responsibilities:
• Top/Block Level Constraints Development: Design and develop constraints at the top and block levels to ensure robust performance and functionality of the design.
• CDC & Lint Checks: Perform Clock Domain Crossing (CDC) and Lint checks to ensure the reliability and accuracy of the design.
• STA Timing Closure: Conduct Static Timing Analysis (STA) to achieve timing closure and meet design specifications.
• SDC Quality Control (QC): Perform quality control on Synopsys Design Constraints (SDC) files to ensure their correctness and efficiency.
• Scripting: Develop and maintain scripts using TCL, Perl, and Python to automate various aspects of the design process.
• Tool Knowledge: Utilize tools such as PrimeTime, Tweaker, and other industry-standard software for design and analysis.
• SDC Writing: Write and optimize SDC files to define timing constraints and guide the design process.
Skills Required:
• STA (Static Timing Analysis):
- Develop constraints from scratch for top-level designs.
- Possess strong timing concepts and the ability to apply them effectively.
- Have a good understanding of tools such as StarRC/PrimeTime or QRC/Tempus.
- Ability to interpret timing reports, analyze and identify timing bottlenecks.
- Exposure to the timing closure flow and methodologies.
• Tools Expertise:
- Proficient in PrimeTime, Spyglass, Tempus, QRC, and STAR-RC.
• Scripting Proficiency:
- Skilled in scripting languages such as TCL, Perl, and Python for automating design processes and enhancing efficiency.
Qualifications:
• BSEE required, MSEE preferred
• Proven experience in STA, SDC writing, and timing closure.
• Strong analytical skills and attention to detail.
• Ability to work independently and as part of a team.
• Excellent problem-solving skills and the ability to troubleshoot complex design issues.
#STA #StaticTimingAnalysis#J-18808-Ljbffr