Nutanix
Network-on-chip/interconnect Design - Staff
Nutanix, Oregon, Illinois, United States, 61061
Company:
Qualcomm India Private LimitedJob Area:
Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:Network-on-chip (NoC)/ Interconnect Design and Architecture for the next generation System-on-chip (SoC) for smartphones, notebooks, smart glasses, tablets and other product categories. The roles and responsibilities for this position includes but not limited to:Design for Next-gen Qualcomm coherent and non-coherent interconnect fabricResponsible for specification, Micro-Arch, design and verification of interconnect and related IP’sActively work with SoC Architecture, verification, physical design team, Soc Floorplan, core teams and various other interconnect teams in various other sitesPartner with SoC performance team ensuring Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptionsResponsible for micro-architecting all relevant debug hooks in NoC Infrastructure to help root cause silicon issuesWill be part of BDC infrastructure (NoC/Interconnect) core teamMinimum Qualifications:8+ years of solid experience in IP/SoC design/VerificationUnderstanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC conceptsGood knowledge of RTL development and verificationHands-on experience with SoC Design, Verilog RTL codingUnderstanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization.Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debugWorking knowledge of Lint, CDC, PLDRC, CLP etcGood understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verificationManage SoC dependencies, planning and tracking of all front-end design related tasksDriving the project milestones across the design, verification and physical implementationsShould possess effective communication and leadership skillsEducation Qualifications:Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
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Qualcomm India Private LimitedJob Area:
Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:Network-on-chip (NoC)/ Interconnect Design and Architecture for the next generation System-on-chip (SoC) for smartphones, notebooks, smart glasses, tablets and other product categories. The roles and responsibilities for this position includes but not limited to:Design for Next-gen Qualcomm coherent and non-coherent interconnect fabricResponsible for specification, Micro-Arch, design and verification of interconnect and related IP’sActively work with SoC Architecture, verification, physical design team, Soc Floorplan, core teams and various other interconnect teams in various other sitesPartner with SoC performance team ensuring Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptionsResponsible for micro-architecting all relevant debug hooks in NoC Infrastructure to help root cause silicon issuesWill be part of BDC infrastructure (NoC/Interconnect) core teamMinimum Qualifications:8+ years of solid experience in IP/SoC design/VerificationUnderstanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC conceptsGood knowledge of RTL development and verificationHands-on experience with SoC Design, Verilog RTL codingUnderstanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization.Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debugWorking knowledge of Lint, CDC, PLDRC, CLP etcGood understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verificationManage SoC dependencies, planning and tracking of all front-end design related tasksDriving the project milestones across the design, verification and physical implementationsShould possess effective communication and leadership skillsEducation Qualifications:Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
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