Tenstorrent Inc
Architecture SOC Architect Santa Clara, California, United States
Tenstorrent Inc, California, Missouri, United States, 65018
The SOC Architect will lead the development, design, and definition of open architecture standards for chiplet products. This position requires a visionary engineer capable of spearheading the design and standardization of modular chiplet interfaces and protocols, collaborating across industries to foster open interoperability standards, and driving innovation in heterogeneous integration. The ideal candidate will have a deep understanding of SoC (System on Chip) design, interconnect protocols, and the semiconductor ecosystem, with a focus on advancing chiplet-based architectures.
This role is Hybrid, based out of Santa Clara, CA.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities:
Define and drive the architecture and development of chiplets, ensuring scalable and interoperable solutions across multiple vendors and applications.
Partner with industry consortiums, research institutions, and standards bodies to establish and promote open chiplet standards and interoperability protocols.
Lead the architectural design and integration of chiplets into heterogeneous systems, focusing on performance, power, and area optimization.
Develop and implement high-performance interconnects and data transmission protocols between chiplets, ensuring efficient communication across the system.
Stay at the forefront of semiconductor industry trends, identify emerging technologies, and integrate advanced concepts into chiplet architectures.
Provide technical guidance and mentorship to engineering teams working on chiplet design, verification, and validation.
Work closely with hardware, software, and packaging teams to ensure seamless integration of chiplets into final products.
Oversee the development of testing methodologies, simulation models, and verification strategies for chiplet-based systems.
Document architecture specifications and design principles, and communicate progress and challenges to stakeholders and leadership teams.
Experience & Qualifications:
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (Master’s or Ph.D. preferred).
10+ years of experience in semiconductor design, with a focus on SoC, chiplet, or modular architectures.
Knowledge of chiplet design, 2.5D/3D packaging, and heterogeneous integration techniques.
Experience in collaborating with industry standards bodies (e.g., OCP, UCIe, IEEE).
Experience in architecting and designing large-scale, high-performance silicon systems.
Knowledge of interconnect standards (e.g., UCIe, PCIe, CXL, HBM).
Knowledge in chiplet communication protocols, power management, and thermal challenges.
Understanding of advanced packaging technologies (e.g., TSVs, interposers).
Understanding of simulation tools and hardware verification techniques.
Strong communication and presentation skills.
Ability to lead cross-functional and industry-wide collaboration.
Problem-solving and analytical mindset.
Proven track record of innovation in semiconductor architecture.
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This role is Hybrid, based out of Santa Clara, CA.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities:
Define and drive the architecture and development of chiplets, ensuring scalable and interoperable solutions across multiple vendors and applications.
Partner with industry consortiums, research institutions, and standards bodies to establish and promote open chiplet standards and interoperability protocols.
Lead the architectural design and integration of chiplets into heterogeneous systems, focusing on performance, power, and area optimization.
Develop and implement high-performance interconnects and data transmission protocols between chiplets, ensuring efficient communication across the system.
Stay at the forefront of semiconductor industry trends, identify emerging technologies, and integrate advanced concepts into chiplet architectures.
Provide technical guidance and mentorship to engineering teams working on chiplet design, verification, and validation.
Work closely with hardware, software, and packaging teams to ensure seamless integration of chiplets into final products.
Oversee the development of testing methodologies, simulation models, and verification strategies for chiplet-based systems.
Document architecture specifications and design principles, and communicate progress and challenges to stakeholders and leadership teams.
Experience & Qualifications:
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (Master’s or Ph.D. preferred).
10+ years of experience in semiconductor design, with a focus on SoC, chiplet, or modular architectures.
Knowledge of chiplet design, 2.5D/3D packaging, and heterogeneous integration techniques.
Experience in collaborating with industry standards bodies (e.g., OCP, UCIe, IEEE).
Experience in architecting and designing large-scale, high-performance silicon systems.
Knowledge of interconnect standards (e.g., UCIe, PCIe, CXL, HBM).
Knowledge in chiplet communication protocols, power management, and thermal challenges.
Understanding of advanced packaging technologies (e.g., TSVs, interposers).
Understanding of simulation tools and hardware verification techniques.
Strong communication and presentation skills.
Ability to lead cross-functional and industry-wide collaboration.
Problem-solving and analytical mindset.
Proven track record of innovation in semiconductor architecture.
#J-18808-Ljbffr