Integrated Circuit (IC) Layout and Mask Design Engineer

MIT Lincoln Laboratory’s Advanced Technology Division develops advanced materials, devices, and subsystems that have broad impact on U.S. Government, industry, and academia. The Division has made a wide range of important contributions during the Laboratory’s 70+ year history, including development of bulk and epitaxial crystal growth, charge-coupled device (CCD) imagers, 193-nm lithography, fully depleted silicon-on-insulator (FDSOI) CMOS electronics, semiconductor diode lasers and amplifiers, superconducting electronics and quantum bit (qubit) devices, and photonic integrated circuits (PICs). To enable this advanced technology development, the Laboratory has implemented vertically integrated in-house resources to facilitate design, lithographic mask layout, material growth and characterization, fabrication (e.g., silicon, compound-semiconductor, wafer bonding, flip-chip hybrid), packaging, and testing of electronic and photonic circuits. These in-house resources are used to fabricate a variety of devices and circuits including lasers, waveguide photodetectors, optical modulators, and CMOS and cryogenic electronics with applications in quantum computing, atomic systems, advanced laser sources, microwave photonics, communications, sensing, and other areas of interest to the U.S. Government, industry, and academia.Job DescriptionThe candidate will work as a member of a multi-disciplinary team responsible for the design and layout of lithographic masks for silicon-based, compound-semiconductor, and heterogeneous/hybrid fabrication processes, especially those for photonic integrated circuits (PICs). The candidate may also work on masks for superconducting qubit and trapped-ion qubit quantum computing, radiation-hard CMOS, and other emerging integrated circuit technologies. The engineer will work in the Cadence environment, with which they should be fluent, and will have responsibility for the full layout project from basic layout cell creation to final tapeout. Key tasks will include coding layout pcells; and laying out devices, test structures, systems, and full mask reticles based on input from device and process designers. They will also be responsible for working with the layout team to update and maintain a device pcell library.Required QualificationsThere is no degree requirement for this positionExperience (> 5 years) with design and layout of lithographic masks used for the fabrication of electronic and/or photonic integrated circuits including:The creation of custom layout blocks and performing layout floor-planningDesign and layout of lithographic masks from devices and test structures to full mask reticlesAbility to work independently with minimal supervision and collaboratively as part of a dynamic, multi-disciplinary teamExcellent organization and intra- and interdisciplinary communication skillsPreferred Qualifications:Bachelor’s or Master’s degree in electrical engineering, computer science, materials science, physics, chemistry, or a related fieldExperience with photonic integrated circuit layout a major plusExperience with or knowledge of one or more of the following areas:Using verification runsets, (ideally with Calibre SVRF or Cadence PVS)The Advanced-Node version of CadenceCadence CurvyCoreProgramming in Perl, TCL, or PythonExperience with RF layout designAt MIT Lincoln Laboratory, our exceptional career opportunities include many outstanding benefits to help you stay healthy, feel supported, and enjoy a fulfilling work-life balance. Benefits offered to employees include:Comprehensive health, dental, and vision plansMIT-funded pensionMatching 401KPaid leave (including vacation, sick, parental, military, etc.)Tuition reimbursement and continuing education programsMentorship programsA range of work-life balance options... and much more!Selected candidate will be subject to a pre-employment background investigation and must be able to obtain and maintain a Secret level DoD security clearance.MIT Lincoln Laboratory is an Equal Employment Opportunity (EEO) employer. All qualified applicants will receive consideration for employment and will not be discriminated against on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, veteran status, disability status, or genetic information; U.S. citizenship is required.Requisition ID:

41417

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