Senior Staff Engineer, Electrical Design

Job DescriptionPropose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated CircuitContribute within a highly experienced team of engineers with extensive cross-functional skill setsEmploy clocking controls, FSM design, low power techniques, and high-speed design conceptsParticipate in design, architecture, and verification reviewsCover digital backend design from synthesis, static timing and logic equivalent checkingCreating documentation targeting design, verification, and test groupsAssisting with new feature proposal, definition, documentation, and implementationMentor and help train junior and New College Grad engineersQualificationsExperience with architecting digital designs and writing device-level or sub-system specificationsExperience in digital design implementation including logical synthesis and DFT insertion with high coverageExperience in static timing analysis and creation of place and route constraintsExperience in formal verification, lint and CDC/RDC checkingExperience in asynchronous clock crossings and synthesis implications of RTLExperience in implementing and verifying ECOs on RTL, synthesized, and post route netlistsFluent in Verilog RTL coding and ASIC design methodology is a mustCompetence in developing design constraints for synthesis, STA and P&R hand-offExperience with gate-level simulations, causes and implications of timing violationsExperience in ATPG generation and ATE support is a plusExperience in DFT or physical design is a plusExperience with Verilog and/or SystemVerilog for digital design and verification is a plusExcellent oral and written communications skills8+ years of direct experience in ASIC/IC design with deep knowledge of whole IC design flowEducationMasters in Electrical Engineering, Computer Engineering, Computer Science, or equivalent with 8+ years of experienceBachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent with 10+ years of experienceCompany DescriptionRenesas is looking for a talented individual for their memory interface products. We are looking for a candidate with a strong background in several areas of integrated circuits (IC) development. These areas are architecture, registered transfer level (RTL) digital design, and design backend. Candidate will work with device specifications and develop digital sections of the device. This candidate needs strong debugging skills to design and create solutions to challenging memory interface issues. Candidate will work closely with applications and test engineering. In addition, strong collaboration and communication skills are a must.Additional InformationThe expected annual pay range for this position is $163,000 - $210,000. This position is also eligible for bonus pay. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate.

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