Memory Performance Architect

Our Client is one of the world’s largest global Top-tier Semiconductor Company. Their chips are used by some of the biggest names in the tech industry, and they are helping to shape the future of technology - thus, making them a major force in the semiconductor industry.

The ideal candidate will become part of the Memory System Design Team, collaborating with architecture, modeling, silicon, software, and other design teams to create a competitive design. We are looking for a proactive individual with experience in enhancing memory performance to optimize memory access behavior in advanced systems.

Role Location: San Jose or San Diego, California

Job Description:

• Experience in computer architecture, microarchitecture, and performance
• Design experience and knowledge in architecture, RTL design, performance analysis, and power optimization.
• Experience in designing and optimizing system-level cache
• Experience DRAM interface standards and memory technologies such as DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.
• Familiarity with system cache, memory controller or DDRPHY for safety, security
• Familiarity with the architecture and the micro-architectures of recent ARM processor is a plus
• Familiarity with AMBA AXI, CHI, and LPDDR4/5 interfaces/protocols is a plus
• Drive Memory System architecture and designs to optimize power, performance, and implementation
• Show system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.)
• Develop and implement tailored Memory Systems. Validate functionality, improve design revisions, and meet performance targets as well as system requirements.

INTERESTED?

We are committed to submitting suitable candidates for this vacancy to our client ASAP, for more information contact Renz Moreno at PER Recruitment or send your CV to renz@per-international.com