Network on Chip Architect

Our client is a leading global semiconductor company, whose chips power major tech industry players and shape the future of technology.

We seek an ideal candidate to join the NoC Interconnect design team, collaborating with architecture, modelling, silicon, software, and other design teams to develop competitive designs. Ideal candidates are hands-on and committed to improving system performance.

Location: San Diego, CA (On-Site)

Job Description:

• Drive NoC Interconnect and Memory System architecture and designs to optimize power, performance, and implementation
• Shows system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.)
• Develop and implement NoC Interconnect for automotive applications. Validate functionality, improve design revisions, and meet performance targets as well as system requirements.
• Ensure that all designs comply with automotive industry standards and regulations, such as ISO 26262 and Automotive SPICE.
• Experience in computer architecture, microarchitecture, and performance
• Experience with automotive requirements and standards (e.g., ISO26262)
• Design experience and knowledge in architecture, RTL design, performance analysis, and power optimization.
• Experience in designing and optimizing interconnect for automotive applications
• Experience in designing the interconnect fail-operational architecture for function safety
• Familiarity with the architecture and the micro-architectures of recent ARM processor is a plus
• Familiarity with AMBA AXI, CHI, and LPDDR4/5 interfaces/protocols is a plus

INTERESTED?

We are committed to submitting suitable candidates for this vacancy to our client ASAP, for more information contact Jacqui Grimwood at PER Recruitment or send your CV to jacqui.g@per-international.com