ASIC EDA Engineer

Will consider relocation.

Open to doing H1 transfers.

• 10+ years of hands-on ASIC engineering experience
• Solid VLSI/SoC chip design and verification workflows
• Exp. with ASIC EDA tool suites from Synopsys and/or Cadence, for physically-aware logic synthesis, RTL and gate-level simulation, structural analysis (CDC, RDC, etc.) and lint tools
• Strong SystemVerilog exp.
• Exp. with C/C++, Perl, TCL and Python
• Experience developing tools for design verification scripting