Della Infotech
Contract Hardware Engineer Mid.
Della Infotech, San Jose, California, United States, 95199
Duties:
Location: San Jose CA (Open for Remote Candidates) Experience: 8+ Years Key Responsibilities Develop and implement comprehensive DFT architectures tailored to specific design requirements. Design and implement robust DFT infrastructure, including scan chains, BIST, and other test mechanisms. Generate high-quality test vectors and analyze DFT coverage to ensure thorough fault detection. Verify test patterns using gate-level simulations to identify and address any functional issues. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related problems. Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. Preferred Qualification Strong understanding of industry standards and best practices in DFT, ATPG, JTAG, and MBIST. Proven experience in developing DFT specifications and architectures for complex designs. Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more. Proficiency in Cadence tools like Modus and Genus for DFT implementation, vector generation, and verification. Ability to conduct experiments during silicon debug, effectively gather and analyze data to identify root causes. Efficient scripting skills using TCL for automating tasks and developing custom flows.
Skills:
Location: San Jose CA (Open for Remote Candidates) Experience: 8+ Years Key Responsibilities Develop and implement comprehensive DFT architectures tailored to specific design requirements. Design and implement robust DFT infrastructure, including scan chains, BIST, and other test mechanisms. Generate high-quality test vectors and analyze DFT coverage to ensure thorough fault detection. Verify test patterns using gate-level simulations to identify and address any functional issues. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related problems. Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. Preferred Qualification Strong understanding of industry standards and best practices in DFT, ATPG, JTAG, and MBIST. Proven experience in developing DFT specifications and architectures for complex designs. Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more. Proficiency in Cadence tools like Modus and Genus for DFT implementation, vector generation, and verification. Ability to conduct experiments during silicon debug, effectively gather and analyze data to identify root causes. Efficient scripting skills using TCL for automating tasks and developing custom flows.
Education:
Bachelors
Required Skills:
DEBUG,SIMULATIONS,JTAG,CADENCE,PHYSICAL DESIGN,Additional Skills:
TCL,SCRIPTING,
Minimum Degree Required:
Bachelor's DegreeHours Per Day:
8.00Hours Per Week:
40.00Languages:
English( Speak, Read, Write )Department:
Cost of goods sold : 1100Job Category:
IT
Location: San Jose CA (Open for Remote Candidates) Experience: 8+ Years Key Responsibilities Develop and implement comprehensive DFT architectures tailored to specific design requirements. Design and implement robust DFT infrastructure, including scan chains, BIST, and other test mechanisms. Generate high-quality test vectors and analyze DFT coverage to ensure thorough fault detection. Verify test patterns using gate-level simulations to identify and address any functional issues. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related problems. Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. Preferred Qualification Strong understanding of industry standards and best practices in DFT, ATPG, JTAG, and MBIST. Proven experience in developing DFT specifications and architectures for complex designs. Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more. Proficiency in Cadence tools like Modus and Genus for DFT implementation, vector generation, and verification. Ability to conduct experiments during silicon debug, effectively gather and analyze data to identify root causes. Efficient scripting skills using TCL for automating tasks and developing custom flows.
Skills:
Location: San Jose CA (Open for Remote Candidates) Experience: 8+ Years Key Responsibilities Develop and implement comprehensive DFT architectures tailored to specific design requirements. Design and implement robust DFT infrastructure, including scan chains, BIST, and other test mechanisms. Generate high-quality test vectors and analyze DFT coverage to ensure thorough fault detection. Verify test patterns using gate-level simulations to identify and address any functional issues. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related problems. Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. Preferred Qualification Strong understanding of industry standards and best practices in DFT, ATPG, JTAG, and MBIST. Proven experience in developing DFT specifications and architectures for complex designs. Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more. Proficiency in Cadence tools like Modus and Genus for DFT implementation, vector generation, and verification. Ability to conduct experiments during silicon debug, effectively gather and analyze data to identify root causes. Efficient scripting skills using TCL for automating tasks and developing custom flows.
Education:
Bachelors
Required Skills:
DEBUG,SIMULATIONS,JTAG,CADENCE,PHYSICAL DESIGN,Additional Skills:
TCL,SCRIPTING,
Minimum Degree Required:
Bachelor's DegreeHours Per Day:
8.00Hours Per Week:
40.00Languages:
English( Speak, Read, Write )Department:
Cost of goods sold : 1100Job Category:
IT