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Michael Page

Trading Platform Developer

Michael Page, New York, New York, us, 10261


Develop A Next Generation Algorithmic Trading PlatformAbove Market Average Compensation PackageAbout Our Client

A financial technology companies that providers an execution management system to instituions using algorithmic trading intelligence.

Job Description

Engineer low-latency, high-performance solutions for reliable, high-volume trading.Contribute to the full software development lifecycle, including design, development, testing, optimization, and maintenance.Optimize system performance through code efficiency, hardware acceleration, and latency reduction.Collaborate with hardware engineers to integrate low-latency hardware solutions.Conduct performance testing and troubleshooting using profiling tools to address inefficiencies.Monitor and maintain platform stability, resolving hardware and software issues.Implement advanced cache optimization and manage CPU resources for maximum efficiency.Stay updated on industry trends to recommend and apply improvements.MPI does not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity or expression, national origin, age, disability, veteran status, marital status, or based on an individual's status in any group or class protected by applicable federal, state or local law. MPI encourages applications from minorities, women, the disabled, protected veterans and all other qualified applicants.

The Successful Applicant

Experience with low-latency messaging protocols and technologies, such as UDP, TCP/IP, or multicast.Proven experience in developing low-latency trading systems or high-frequency trading platforms using hardware acceleration techniques.Proficiency in low-latency Java libraries such as Chronical, Eclipse, JCTools, etc.Knowledge of algorithmic trading strategies, order types, market microstructure, and electronic trading platforms.Familiarity with hardware acceleration technologies, hardware description languages (e.g., Verilog, VHDL), and hardware-software co-design.Understanding of cache coherence protocols and cache optimization techniques for low-latency data access.Experience with CPU affinity, thread management, and multi-core optimization for high-performance computing.Exceptional programming skills with a focus on performance optimization and hardware integration.BS/BA degree or higher in Computer Science and/or Engineering, or equivalent experienceWhat's on Offer

Above market average base salaryAnnual discretionary cash bonusHybrid work enviornment with a top tier office in the financial districtFull comprehensive healthcare packagePaid-time-off401k match programAdditional work life balance benefits

Contact

Maximus Egermayer

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JN-102024-6553658