Harris Allied
Senior Engineer/Electronic Trading
Harris Allied, New York, New York, United States, 10001
Global financial services industry leader has an immediate need for a Senior Engineer with experience building low latency, electronic trading platforms, and infrastructure to join their growing Algorithmic Trading Platform team. They will contribute to the delivery of high-availability, low-latency technology supporting client-facing trading algorithms, smart order routing, trader workflows, and will partner with Algo Developers, Product, and Technology teams to deliver best-in class trading solutions for institutional traders on a global basis.This individual will have current trading solutions development experience including solid hands-on Java skills and experience building and optimizing low-latency trading systems using hardware acceleration, GC free programming, quantitative analytics, market signal events, and statistical analysis.
ResponsibilitiesCreate and engineer solutions that achieve ultra-low latency performance, seamlessly accommodating high-volume trading days, while maintaining reliability and data integrity.Contribute to the SDLC including design, development, integration, automated testing, optimization, and maintenance.Optimize trading system performance by minimizing latency, optimizing code execution, and leveraging hardware acceleration.Partner with hardware engineers to design and integrate low-latency hardware solutions, such as accelerators and network cards.Conduct performance testing and analysis using hardware and software profiling tools such as JVisualVM, JProfiler, or YourKit to identify and address bottlenecks and inefficiencies.Monitor and maintain the stability and reliability of the trading platform, including troubleshooting and resolving technical issues related to hardware and software interactions.Integrate advanced cache coherence methodologies and fine-tune cache usage across L1, L2, and L3 caches to significantly boost data retrieval efficiency and drastically decrease latency within the system.Optimize the utilization of hardware resources by strategically managing CPU affinity and thread scheduling in multi-core environments.
ExperienceProven experience (7+ years) in developing low-latency trading systems or high-frequency trading platforms using hardware acceleration and performance optimization.Proficiency with low-latency Java libraries such as Chronicle and other specialized Java collections like Eclipse, JCTools, etc., demonstrating a deep understanding of efficient data handling and processing in high-performance computing environments.In-depth knowledge of GC-free programming techniques, including object reuse, memory management, lock-free data structures, and minimizing memory allocations.Knowledge of algorithmic trading strategies, order types, market microstructure, and electronic trading platforms.Understanding of cache coherence protocols and cache optimization techniques for low-latency data access.Experience with CPU affinity, thread management, and multi-core optimization for high-performance computing.Experience with low-latency messaging protocols and technologies, such as UDP, TCP/IP, or multicast.
ResponsibilitiesCreate and engineer solutions that achieve ultra-low latency performance, seamlessly accommodating high-volume trading days, while maintaining reliability and data integrity.Contribute to the SDLC including design, development, integration, automated testing, optimization, and maintenance.Optimize trading system performance by minimizing latency, optimizing code execution, and leveraging hardware acceleration.Partner with hardware engineers to design and integrate low-latency hardware solutions, such as accelerators and network cards.Conduct performance testing and analysis using hardware and software profiling tools such as JVisualVM, JProfiler, or YourKit to identify and address bottlenecks and inefficiencies.Monitor and maintain the stability and reliability of the trading platform, including troubleshooting and resolving technical issues related to hardware and software interactions.Integrate advanced cache coherence methodologies and fine-tune cache usage across L1, L2, and L3 caches to significantly boost data retrieval efficiency and drastically decrease latency within the system.Optimize the utilization of hardware resources by strategically managing CPU affinity and thread scheduling in multi-core environments.
ExperienceProven experience (7+ years) in developing low-latency trading systems or high-frequency trading platforms using hardware acceleration and performance optimization.Proficiency with low-latency Java libraries such as Chronicle and other specialized Java collections like Eclipse, JCTools, etc., demonstrating a deep understanding of efficient data handling and processing in high-performance computing environments.In-depth knowledge of GC-free programming techniques, including object reuse, memory management, lock-free data structures, and minimizing memory allocations.Knowledge of algorithmic trading strategies, order types, market microstructure, and electronic trading platforms.Understanding of cache coherence protocols and cache optimization techniques for low-latency data access.Experience with CPU affinity, thread management, and multi-core optimization for high-performance computing.Experience with low-latency messaging protocols and technologies, such as UDP, TCP/IP, or multicast.