Lead Design Verification

Design Verification/ Responsibilities:Develop verification methodology and testbenches for digital and mixed-signal blocksTest plan, coverage analysis and closure for parallel link and SerDes IP blocks and on-chip interconnectsBasic Qualifications:BS, MS in Electrical Engineering, Computer Engineering, or related fieldsExperience:Local US lead is expected to have 10+ years of work experience in ASIC design verificationOther engineers expected to have 2 to 5 years of work or academic experience in ASIC design verificationHistory of assuming responsibility for a variety of technical tasks and completing projects independentlyProficient in System Verilog, UVM testbench development for design verification of complex digital and PHY blocks (in AMS and WREAL modeling verification)Proficient in pre-synthesis, and post- place-and-route functional verification (NCSIM, VCS,ModelSim)Proficient in scripting or programming languagesExperience working with version control software, such as GitPreferred Qualifications:Experience working on digital designs with multiple clock domains and clock dividersExperience in verification of SerDes IP block interfaces in a complex SoC fabric environmentExperience in verification of the PCS, PMA SerDes layers and internal SerDes digital backendsExperience with verification of HBM memory interfaces (PHY and controller)Experience in formal model equivalence checking tools and verification methodologyProgramming experience in Python