Sr. Silicon Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming, and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.THE ROLE:AMD's Adaptive and Embedded Computing Group (AECG) is seeking a Senior Silicon Design Verification Engineer, who can provide technical leadership and contribution on Verification of Network-on-Chip (NoC) and high-speed Memory Controller IPs. The individual will help design, develop, and use simulation and/or formal based verification environments, at block and full-chip level, to prove the functional correctness of Network-on-Chip (NoC), System-level Quality of Service (QoS), and DDR, LPDDR, and HBM Memory Controller IP designs.THE PERSON:A Senior Design Engineer will be a dynamic, quality-conscious, attention-oriented individual with significant experience in successfully verifying products with high quality. Your experience and expertise in developing advanced SystemVerilog and UVM based testbench and Automation that can scale with Full-Chip will enable improved execution of AMD's devices and productivity. Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.KEY RESPONSIBILITIES:Collaborate with Architecture, Design, and Software teams to prove that the system-level architecture requirements are met as part of Pre-Silicon Functional Verification.Work includes Test Planning, testbench architecture, execution, tracking, coverage closure, and delivery to programs.Create Testbench Architecture.PREFERRED EXPERIENCE:Requires strong understanding of AXI protocol, NoC architecture, DRAM memory controllers, especially DDR4/5, LPDDR4/5, and HBM2/2E/3.Requires experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify Full-Chip FPGA designs and memory controller IPs.Requires strong understanding of state of the art verification techniques, including assertion and coverage-driven verification. Experience as a verification architect, establishing the verification methodology, tools, and infrastructure for high-performance IP and/or VLSI designs is a plus.Requires familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.Experience with FPGA programming and software is a plus.Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.Experience with gate-level simulation, power-aware verification, reset verification, contention checking is a plus.Experience with silicon debug at the tester and board level is a plus.ACADEMIC CREDENTIALS:Requires BS, MS, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.LOCATION:

San Jose, CA#LI-DW1#LI-HYBRID

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