Senior Principal Design Verification Engineer (Hybrid)

**Job Description**Are you interested in quantum imaging? Join us! In this role you can apply your expertise in Front End Digital design for ASICs driving our latest sensors highlighted by their low read noise capabilities. This involves architecting and implementing digital functions of sensors and validating the products through programming the bring-up systems to achieve world class performance. Your work will enable our cutting-edge imaging products.The Imaging Solutions organization of BAE Systems is part of our Microelectronics product line in FAST Labs. Imaging Solutions has a strong history of driving innovation in imaging for commercial applications. Innovation ranges from the first commercial CCD imager in 1970 to applications including the Hubble Telescope, cinematic cameras and state of the art scientific imaging. As a small organization within a large corporation we enjoy the diversity and comradery of a start up with the stability of a large company.Detail requirements:+ Solid understanding of verification methodologies, especially UVM (SystemVerilog (SV)), including:+ Test planning+ Test bench creation+ Code and Functional coverage+ Directed and random stimulus generation+ Assertions+ Regression triage+ Defining detailed test plan and implementing Verilog simulation test cases to verify design functionality.+ Build verification environment using SV/UVM methodology+ Build reusable bus functional models, monitors, checkers and scoreboards+ Debug product, test and resolve design issues+ Integration of VIP cores Buses, Controllers, PHYs, etc with other logic within ASIC/FPGABecause this role involves a combination of collaborative/in-person and independent work, it will take the form of a **hybrid work format** , with time split between working onsite and remotely.**Required Education, Experience, & Skills**+ Typically a BS with 10 years of experience or MS with 8 years of experience.+ Desired majors Electrical Engineering, Computer Engineering, or Computer Science+ Proficient in SystemVerilog (SV) language for ASIC design, and related FPGA+ Knowledge of ASIC design flows is highly desirable, and FPGA is a plus+ Knowledge simulation and verification methodologies (Cadence/Synopsys tool simulator, UVM)+ Excellent organization and communication skills for interacting between different design groups+ Proficiency in C/C and scripting languages is a plus**Preferred Education, Experience, & Skills**+ BS in EE or Computer Science, MS or Doctoral degree preferred+ 10 years of experience in ASIC/FPGA Development (Verilog, System Verilog, UVM**Pay Information**Full-Time Salary Range: $147300 - $250400Please note: This range is based on our market pay structures. However, individual salaries are determined by a variety of factors including, but not limited to: business considerations, local market conditions, and internal equity, as well as candidate qualifications, such as skills, education, and experience.Employee Benefits: At BAE Systems, we support our employees in all aspects of their life, including their health and financial well-being. Regular employees scheduled to work 20 hours per week are offered: health, dental, and vision insurance; health savings accounts; a 401(k) savings plan; disability coverage; and life and accident insurance. We also have an employee assistance program, a legal plan, and other perks including discounts on things like home, auto, and pet insurance. Our leave programs include paid time off, paid holidays, as well as other types of leave, including paid parental, military, bereavement, and any applicable federal and state sick leave. Employees may participate in the company recognition program to receive monetary or non-monetary recognition awards. Other incentives may be available based on position level and/or job specifics.**Senior Principal Design Verification Engineer (Hybrid)****106128BR**EEO Career Site Equal Opportunity Employer. Minorities . females . veterans . individuals with disabilities . sexual orientation . gender identity . gender expression