CV Library
Design Verification Engineer
CV Library, Burlingame, California, United States, 94012
Title:
Design Verification Engineer Location:
Burlingame, CA - (Remote) - Candidates in Pacific time zone will be considered Type:
Contract Duration:
12+ Months Note:
We are looking for a Design Verification Engineer with 5-15 years of relevant experience. Responsibilities:
Understanding of Ethernet / project specifications. Writing Test plan and coverage plan. Write test cases/scenarios. Update existing testbench components like generators, drivers, and monitors. Debug existing tests failing in the regression. Work on Subsystem and system level verification. Mandatory Qualifications:
5+ years of proven experience as a DV engineer. Hands-on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology). Hands-on experience with Synopsys VCS / Verdi or Cadence Incisive tools. Experience with UPF based simulation flow. 2+ years of experience with C/C++. Tcl and Python (or similar) scripting. Nice to Have:
Power and performance FPGA validation. Python scripting. Experience with Power Aware GLS flow. ASIC design experience. Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators. Experience with complex SoCs. Knowledge of coverage merging across simulation and formal.
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Design Verification Engineer Location:
Burlingame, CA - (Remote) - Candidates in Pacific time zone will be considered Type:
Contract Duration:
12+ Months Note:
We are looking for a Design Verification Engineer with 5-15 years of relevant experience. Responsibilities:
Understanding of Ethernet / project specifications. Writing Test plan and coverage plan. Write test cases/scenarios. Update existing testbench components like generators, drivers, and monitors. Debug existing tests failing in the regression. Work on Subsystem and system level verification. Mandatory Qualifications:
5+ years of proven experience as a DV engineer. Hands-on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology). Hands-on experience with Synopsys VCS / Verdi or Cadence Incisive tools. Experience with UPF based simulation flow. 2+ years of experience with C/C++. Tcl and Python (or similar) scripting. Nice to Have:
Power and performance FPGA validation. Python scripting. Experience with Power Aware GLS flow. ASIC design experience. Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators. Experience with complex SoCs. Knowledge of coverage merging across simulation and formal.
#J-18808-Ljbffr