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Design Verification Engineer
https:/www.energyjobline.com/sitemap.xml, San Jose, California, United States, 95199
JOB TITLE: Design Verification Engineer
LOCATION: San Jose, CA
DURATION: 1 year
PAY RANGE: $80.00 - $120.00/hr
TOP 3 SKILLS:
Proficient in System Verilog/UVM/OVM, OOP/C++
Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
Experience with code coverage and functional coverage driven verification methodology.
COMPANY:
Our client, a multinational electronics company is recruiting for a Design Verification Engineer. If you meet the qualifications listed, please Apply Now!
Description:
As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.
Responsibilities
" Triage regression failures and make testbench updates
" Debug functional errors in RTL model using simulation and debug tools.
" Maintain efficient and clean regression status
" Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.
" Review Architecture and Micro-Architecture specifications.
" Closely work with Architects and RTL designers.
" Define, maintain and execute unit level and/or Cluster level verification testplans.
" Generate and run Testcases on logic simulation models.
" Code Functional coverage models and System Verilog assertions.
" Drive Functional Coverage and Code coverage to closure.
" Integrate C++ reference model into Scoreboards
Requirements:
" 5-15 year's industry experience in a design verification role.
" Proficient in System Verilog/UVM/OVM, OOP/C++
" Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
" Experience with code coverage and functional coverage driven verification methodology.
" Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench.
" Excellent working knowledge of scripting
such as Python or Perl.
" Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines.
" Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.
" Strong debugging skills
" Strong programming skills with good understanding of algorithms and data structures
" Good verbal and written communication skills.
IND 123
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LOCATION: San Jose, CA
DURATION: 1 year
PAY RANGE: $80.00 - $120.00/hr
TOP 3 SKILLS:
Proficient in System Verilog/UVM/OVM, OOP/C++
Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
Experience with code coverage and functional coverage driven verification methodology.
COMPANY:
Our client, a multinational electronics company is recruiting for a Design Verification Engineer. If you meet the qualifications listed, please Apply Now!
Description:
As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.
Responsibilities
" Triage regression failures and make testbench updates
" Debug functional errors in RTL model using simulation and debug tools.
" Maintain efficient and clean regression status
" Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.
" Review Architecture and Micro-Architecture specifications.
" Closely work with Architects and RTL designers.
" Define, maintain and execute unit level and/or Cluster level verification testplans.
" Generate and run Testcases on logic simulation models.
" Code Functional coverage models and System Verilog assertions.
" Drive Functional Coverage and Code coverage to closure.
" Integrate C++ reference model into Scoreboards
Requirements:
" 5-15 year's industry experience in a design verification role.
" Proficient in System Verilog/UVM/OVM, OOP/C++
" Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
" Experience with code coverage and functional coverage driven verification methodology.
" Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench.
" Excellent working knowledge of scripting
such as Python or Perl.
" Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines.
" Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.
" Strong debugging skills
" Strong programming skills with good understanding of algorithms and data structures
" Good verbal and written communication skills.
IND 123
#J-18808-Ljbffr