Indeed
Senior E/E & Semiconductor Engineer - Lead DV IP Verification Engineer
Indeed, San Francisco, California, United States, 94199
Job Role:
Lead DV IP Verification EngineerJob Location:
San Francisco CA / Sunnyvale CAJob Description:
Architect and create verification environments using System-Verilog and UVM (Universal Verification) methodology for IP verification. IP verification is a must, and SoC verification is good to have.Key Responsibilities
SystemVerilog/UVM/C++/PythonRequired Skills
Proficiency and proven work experience in UVM & System Verilog based DV development.Strong knowledge in SV Assertions, UVM/OVM and functional and code coverage analysis.Python scripting experience.C/C++ based reference model debug experience.Strong regression failure and root cause analysis.Independent, self-motivated with good analytical & communication skills.About Capgemini Engineering
Capgemini Engineering is a world leader in engineering and R&D services, combining broad industry knowledge and cutting-edge technologies to support the convergence of the physical and digital worlds.Benefits
Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:Flexible workHealthcare including dental, vision, mental health, and well-being programsFinancial well-being programs such as 401(k) and Employee Share Ownership PlanPaid time off and paid holidaysPaid parental leaveFamily building benefits like adoption assistance, surrogacy, and cryopreservationSocial well-being benefits like subsidized back-up child/elder care and tutoringMentoring, coaching, and learning programsEmployee Resource GroupsDisaster ReliefDisclaimer
Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
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Lead DV IP Verification EngineerJob Location:
San Francisco CA / Sunnyvale CAJob Description:
Architect and create verification environments using System-Verilog and UVM (Universal Verification) methodology for IP verification. IP verification is a must, and SoC verification is good to have.Key Responsibilities
SystemVerilog/UVM/C++/PythonRequired Skills
Proficiency and proven work experience in UVM & System Verilog based DV development.Strong knowledge in SV Assertions, UVM/OVM and functional and code coverage analysis.Python scripting experience.C/C++ based reference model debug experience.Strong regression failure and root cause analysis.Independent, self-motivated with good analytical & communication skills.About Capgemini Engineering
Capgemini Engineering is a world leader in engineering and R&D services, combining broad industry knowledge and cutting-edge technologies to support the convergence of the physical and digital worlds.Benefits
Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:Flexible workHealthcare including dental, vision, mental health, and well-being programsFinancial well-being programs such as 401(k) and Employee Share Ownership PlanPaid time off and paid holidaysPaid parental leaveFamily building benefits like adoption assistance, surrogacy, and cryopreservationSocial well-being benefits like subsidized back-up child/elder care and tutoringMentoring, coaching, and learning programsEmployee Resource GroupsDisaster ReliefDisclaimer
Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
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