Capgemini
Senior E/E & Semiconductor Engineer - Lead DV IP Verification Engineer
Capgemini, San Francisco, California, United States, 94199
Job role:
Lead DV IP Verification EngineerJob Location:
San Francisco CA / Sunnyvale CAJob description:Architect and create verification environments using System-Verilog and UVM (Universal verification) methodology for IP verification. IP verification must have and SoC verification is good to have.
Key responsibilities
SystemVerilog/UVM/C++/Python
Required Skills
Proficiency and proven work experience in UVM & System Verilog based DV development.
Strong knowledge in SV Assertions, UVM/OVM and functional and code coverage analysis.
Python scripting experience.
C/C++ based reference model debug experience.
Strong regression failure and root cause analysis.
Independent, self-motivated with good analytical & communication skills.
Life at CapgeminiCapgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:
Flexible work.
Healthcare including dental, vision, mental health, and well-being programs.
Financial well-being programs such as 401(k) and Employee Share Ownership Plan.
Paid time off and paid holidays.
Paid parental leave.
Family building benefits like adoption assistance, surrogacy, and cryopreservation.
Social well-being benefits like subsidized back-up child/elder care and tutoring.
Mentoring, coaching and learning programs.
Employee Resource Groups.
Disaster Relief.
About Capgemini EngineeringWorld leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds.
DisclaimerCapgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
Applicants for employment in the US must have valid work authorization that does not now and/or will not in the future require sponsorship of a visa for employment authorization in the US by Capgemini.
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Lead DV IP Verification EngineerJob Location:
San Francisco CA / Sunnyvale CAJob description:Architect and create verification environments using System-Verilog and UVM (Universal verification) methodology for IP verification. IP verification must have and SoC verification is good to have.
Key responsibilities
SystemVerilog/UVM/C++/Python
Required Skills
Proficiency and proven work experience in UVM & System Verilog based DV development.
Strong knowledge in SV Assertions, UVM/OVM and functional and code coverage analysis.
Python scripting experience.
C/C++ based reference model debug experience.
Strong regression failure and root cause analysis.
Independent, self-motivated with good analytical & communication skills.
Life at CapgeminiCapgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:
Flexible work.
Healthcare including dental, vision, mental health, and well-being programs.
Financial well-being programs such as 401(k) and Employee Share Ownership Plan.
Paid time off and paid holidays.
Paid parental leave.
Family building benefits like adoption assistance, surrogacy, and cryopreservation.
Social well-being benefits like subsidized back-up child/elder care and tutoring.
Mentoring, coaching and learning programs.
Employee Resource Groups.
Disaster Relief.
About Capgemini EngineeringWorld leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds.
DisclaimerCapgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
Applicants for employment in the US must have valid work authorization that does not now and/or will not in the future require sponsorship of a visa for employment authorization in the US by Capgemini.
#J-18808-Ljbffr