Cadence Design Systems
Principal Design Engineer
Cadence Design Systems, Austin, Texas, us, 78716
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Principal Design Engineer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Principal Mixed-Signal Verification and Emulation Engineer is responsible for defining and implementing mixed-signal solutions, verification plans, models, roadmaps and delivering complete Mixed-Signal DV and emulation solutions that address challenges across the full spectrum of diverse mixed-signal products. This also includes driving innovation across the Mixed-Signal verification flow to create efficient and accurate mixed-signal methodologies and improve verification of SERDES controller and phy through emulation with Palladium/Protium.
This ideal candidate is expected to be a mixed-signal DV expert or emulation expert and will be the hub between all engineering teams.
Duties:
Architect, develop, champion, and implement metric-driven mixed-signal verification solutions, in the areas of: Digital/DMS/AMS/Emulation testbench creation and generation
Automatic Model generation and testing
Cadence Design Systems AMS simulation flows
Mixed-Signal Assertions and Checkers
Synthesizable and Non-Synthesizable Behavioral Modeling and Model Validation Methodologies
Mixed-Signal VIP integration and testing
Mixed-Signal emulation flows and practices
Power intent verification including Low power states, state retention, and CPF/UPF integration
Push technology for mixed-signal modeling, simulation, and DV in order to improve mixed-signal verification efficiency and accuracy.
Ensure scalable mixed-signal DV solutions to cover the breadth of IPG offerings including SerDes, DDR, A2D converters, and custom solutions
Drive adoption of analog behavioral modeling methodologies for efficient mixed-signal verification from conception through simulation and emulation
Develop efficient debug solutions and techniques
Develop an efficient and accurate full-stack mixed-signal methodology for the entire IP stack from the controller to the analog circuit.
Propagate mixed-signal knowledge and mentor junior engineers
Collaborate closely with:
Digital, Analog, Firmware, Test and customer engineers
Internal methodology and tool development teams, like Virtuoso/ADE/Xcelium/Palladium/Protium. PDK teams
Customer management and engineering support teams
Qualifications
7-15+ Years’ experience in working with Digital and Analog mixed-signal environments and teams.
Must have good written and verbal cross-functional communication skills.
Proven experience in most of the following:
Creating Verification infrastructure (test-bench, environment, scripting)
Scripting of verification flows, design automation
Debugging verification test cases
Knowledge of existing and upcoming standards such as PCIE, USB, DDR4, etc.
Must be comfortable interacting across the IPG development team including the ability to understand design constraints.
Knowledge of multiple programming languages. C++, Python, System Verilog, and e (verification language) are a plus
Knowledge of Mixed-Signal Cadence tools and mixed-signal methodology is a plus
Knowledge of Palladium/Protium or other hardware accelerator tools is a plus.
Knowledge of System Verilog and UVM Test environment and methods is a plus
Working knowledge of revision control tools such as SOS, SVN is a plus
Education Level: Bachelor's Degree (MSEE Preferred)
We’re doing work that matters. Help us solve what others can’t.
We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.
Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl_jobs)
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Principal Design Engineer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Principal Mixed-Signal Verification and Emulation Engineer is responsible for defining and implementing mixed-signal solutions, verification plans, models, roadmaps and delivering complete Mixed-Signal DV and emulation solutions that address challenges across the full spectrum of diverse mixed-signal products. This also includes driving innovation across the Mixed-Signal verification flow to create efficient and accurate mixed-signal methodologies and improve verification of SERDES controller and phy through emulation with Palladium/Protium.
This ideal candidate is expected to be a mixed-signal DV expert or emulation expert and will be the hub between all engineering teams.
Duties:
Architect, develop, champion, and implement metric-driven mixed-signal verification solutions, in the areas of: Digital/DMS/AMS/Emulation testbench creation and generation
Automatic Model generation and testing
Cadence Design Systems AMS simulation flows
Mixed-Signal Assertions and Checkers
Synthesizable and Non-Synthesizable Behavioral Modeling and Model Validation Methodologies
Mixed-Signal VIP integration and testing
Mixed-Signal emulation flows and practices
Power intent verification including Low power states, state retention, and CPF/UPF integration
Push technology for mixed-signal modeling, simulation, and DV in order to improve mixed-signal verification efficiency and accuracy.
Ensure scalable mixed-signal DV solutions to cover the breadth of IPG offerings including SerDes, DDR, A2D converters, and custom solutions
Drive adoption of analog behavioral modeling methodologies for efficient mixed-signal verification from conception through simulation and emulation
Develop efficient debug solutions and techniques
Develop an efficient and accurate full-stack mixed-signal methodology for the entire IP stack from the controller to the analog circuit.
Propagate mixed-signal knowledge and mentor junior engineers
Collaborate closely with:
Digital, Analog, Firmware, Test and customer engineers
Internal methodology and tool development teams, like Virtuoso/ADE/Xcelium/Palladium/Protium. PDK teams
Customer management and engineering support teams
Qualifications
7-15+ Years’ experience in working with Digital and Analog mixed-signal environments and teams.
Must have good written and verbal cross-functional communication skills.
Proven experience in most of the following:
Creating Verification infrastructure (test-bench, environment, scripting)
Scripting of verification flows, design automation
Debugging verification test cases
Knowledge of existing and upcoming standards such as PCIE, USB, DDR4, etc.
Must be comfortable interacting across the IPG development team including the ability to understand design constraints.
Knowledge of multiple programming languages. C++, Python, System Verilog, and e (verification language) are a plus
Knowledge of Mixed-Signal Cadence tools and mixed-signal methodology is a plus
Knowledge of Palladium/Protium or other hardware accelerator tools is a plus.
Knowledge of System Verilog and UVM Test environment and methods is a plus
Working knowledge of revision control tools such as SOS, SVN is a plus
Education Level: Bachelor's Degree (MSEE Preferred)
We’re doing work that matters. Help us solve what others can’t.
We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.
Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl_jobs)
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.