Senior Engineer - Digital Design (Japan)

Senior Engineer (Japan) – Digital Design A company differentiates from the old quartz timing industry, number one in the world for oscillator supply, having 3,000,000 devices in over 300 applications, is seeking professionals to join their team in Japan. My client is now looking for a Senior Engineer in Digital Design to join their team. As a Senior Engineer, Digital Design, your role will be responsible for: Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD). Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or System Verilog as the HDL. Developing standalone testbenches to verify the RTL behaviour. Writing and verifying System Verilog Assertions (SVA) for a design. Salary ranged from JPY$ 8-20M Yen depending on ability. Requirements: Master’s degree in electrical engineering plus 5 years of relevant work experience in the industry. Excellent verbal and written communication skills in English. Proficient in Verilog and System Verilog. Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc. Experience in designing mixed-signal digital logic. Basic understanding of Discrete time Signal Processing theory, FIR and IIR filter design. Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA. Skilled in scripting languages Perl/Tcl/Python. Please feel free to contact Simpson at IC Resources if you are interested in this Senior Engineer, Digital Design opening or any other opportunities available.

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