SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.RESPONSIBILITIES:Develop/support automated block and full chip level advanced timing/noise signoff flows (with advanced and parametric on chip variation, and voltage drop aware STA)Define block and full chip timing signoff criterion, methodology, constraints, modes and scenarios and close timing at multi-corner and multi-mode environmentsDevelop/support signoff STA timing/power optimization engineering change order flows (Timing ECOs) and integrate them into physical design flowWork with systems and architecture, SOC integration, verification, DFT, mixed signal, IP owners, synthesis, and place/route teams to address the design challenges in the context of timing sign-offGenerate block timing budgets, clock and I/O context filesDebug and drive fixing of constraint correlation issues between top and block levelDevelop clock network simulation and jitter analysis methodologiesBASIC QUALIFICATIONS:Bachelor’s degree in electrical engineering, computer engineering or computer scienceExperience in static timing analysis and/or timing closure of high-performance SOC designsPREFERRED SKILLS AND EXPERIENCE:Full chip and block level STA tapeout experience, constraint generation and partitioningKnowledge of deep sub-micron FinFET technology nodes (7nm and below) timing challenges, multi-corner and multimode timing closure, process variations, voltage drop aware STA, and CRPRExperience with memories, I/Os, Analog IPs, SerDes, DDR, etc. preferredExperience in industry standard STA and Noise/Signal integrity analysis toolsExperience in clock jitter simulation and analysis methodologiesExperience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on physical design and timing closureFamiliar with ASIC synthesis and physical design flows and methodologiesExperience with high reliability design and implementationsExcellent scripting skills (csh/bash, Perl, Python, TCL, Makefile, etc.)Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environmentADDITIONAL REQUIREMENTS:Must be willing to travel when needed (typically