Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Enginee

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING)At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to 3M+ users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.    RESPONSIBILITIES:Full chip and block level timing signoff and convergence through timing ecos on post routed database for various timing signoff checksFull chip and block level front-end implementation from timing constraints development, synthesis, formal verification, power intent generation & validationDevelop block and full chip level timing constraints for test modesTiming closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)Analysis of clock domain crossing paths at block and full chip levelWork with mixed signal IP/PLL/SerDes/PHY teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTLDevelop/modify/run RTL logic synthesis, formal verification, power intent verification and post synthesis timing validation flowsExecute low power design and physical synthesis, deploying knowledge of unified power format and power intent verificationImplement Functional ECOs for complex blocksDeploy and enhance methodology and flows related to timing constraint generation and verification and timing closureWork closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs – generally bridging the RTL and place and routeWork with multi-disciplinary groups to make sure RTL/Netlists are on schedule and delivered with the highest quality by incorporating automated checks at every stage of the design processBASIC QUALIFICATIONS:Bachelor’s degree in electrical engineering, computer engineering or computer science5+ years of experience working as a synthesis and/or front-end STA engineerPREFERRED SKILLS AND EXPERIENCE:Experience in ASIC multimode constraint generation, constraint partitioning and timing closure in advanced nodesExperience with test modes, mode merging to optimize physical design implementation and STA Signoff.Experience with power intent and upf development for block and soc top.Familiar with formal verification and implementing functional ecos.Knowledge of deep sub-micron FinFET technology nodes (7nm and below) timing challenges, multi-corner and multimode timing closure, process variations (AOCV, POCV based STA), voltage drop aware STA, and clock reconvergence pessimism removalHands-on experience in industry standard physical synthesis and STA tools (Synopsys DC, Primetime or equivalent)Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closureDeep understanding of ASIC design flow, top-down and bottom-up design methodologiesKnowledge of low-power methodologies and leakage/dynamic power optimization flows and techniquesFamiliar with implementation or integration of design blocks using Verilog/SystemVerilogExperience with high reliability design and implementationsExcellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment  ADDITIONAL REQUIREMENTS:Must be willing to travel when needed (typically