Principal Layout Engineer

Principal Layout Engineer

Job Type: Full-Time

Location: CA - San Jose, US

Requisition ID: 8424

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves diverse high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our diverse and innovative team is helping connect, protect and power our planet.

Qorvo’s fast-growing Power Management division focusing on Power loss protection, PMICs, Motor Control, and Battery Management solutions for a wide range of Mobile, Consumer, IOT and Industrial applications is looking for an experienced Principal Layout Engineer.

Responsibilities:

1. Layout of Power and Analog integrated circuits for the general power electronics market (mobile, industrial, consumer)
2. Floor planning and concept realization of highly integrated analog/power circuits
3. Top Level and block level layout designs including circuit and layout verification checks (LVS, DRC)
4. Full Analogue layout design and layout size optimization of CMOS JI and SOI
5. Interface and cooperation with Analog and Power IC design engineers in Asia and US
6. Responsibility for tape out process, data documentation and data archiving
7. Independent interface with design engineering, foundry and manufacturing

Qualifications:

1. 15+ years of relevant work experience
2. Fluency in Vietnamese preferred.
3. Background in analog power IC fundamentals and experience with integrated analog mixed-signal circuit layouts
4. 8+ years in Layout experience in Virtuoso integrated circuit environment.
5. 4+ years in inductive DC/DC (buck, boost, bubo) layout design.
6. 5+ years’ experience in BCD processes where LDMOS were used.
7. 4 projects where you laid out power FETs for optimal RDS metallization.
8. Led at least one layout development using contractors.
9. Familiar with Guard Ring structures, electromigration design requirements, WPE effects, LVS, DRC, GDS send to fab, WCSP, BGA, Calibre.
10. Understanding of semiconductor process technologies like CMOS JI, and SOI
11. Experience working with voltages in 5-200V range is preferred.
12. Experience with CAD layout tools like Cadence
13. Outstanding Analytical and problem-solving skills
14. Well-developed interpersonal and communication skills

Qorvo will not sponsor visas for this position.

Competitive base salary commensurate with experience: $182,100 - $236,800, relevant for the California Bay Area (subject to change dependent on physical location).

Posted salary ranges are made in good faith. Qorvo reserves the right to adjust ranges depending on the experience/qualification of the selected candidate as well as external competitiveness and internal comparability. Base compensation is one element of Total Rewards offered at Qorvo. More information on the Total Rewards package can be shared upon request.

MAKE A DIFFERENCE AT QORVO

We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.

We are an Equal Employment Opportunity (EEO) / Affirmative Action employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, military or veteran status, physical or mental disability, genetic information, and/or any other status protected by law.

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