Qualcomm
Digital design engineer
Qualcomm, Santa Clara, California, us, 95053
Company:
Qualcomm Atheros, Inc. Job Area:
Engineering Group, Engineering Group > ASICS Engineering General Summary: Working with the WiFi algorithm and systems team to design and test advanced WiFi functionalities such as OFDM and OFDMA modulators and demodulators, transmit beamforming, timing and synchronization, RF impairment correction, adaptive filters. Working with the algorithms/systems/modeling team to obtain a fixed-point/finite-precision C/C++ model that is realizable in optimized ASIC hardware. Converting the finite-precision models into ASIC hardware using SystemC/C++ for HLS (High-Level Synthesis) as the primary hardware description language that meet the area and power targets. Working with the verification engineers to develop unit-level and integrated-level test-benches. Debugging the designs in stand-alone and integrated with the system. Synthesis and gate-level timing tasks related to the designed module and assist with verification and timing of the entire chip. Design quality check such as lint, CDC and low power rule checks. RTL-level and gate-level vector-based power analysis. Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Preferred Qualifications: Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. 9+ years of ASIC design, verification, validation, integration, or related work experience. 3+ years of experience with architecture and design tools. 3+ years of experience with scripting tools and programming languages. 3+ years of experience with design verification methods. 2+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above). Principal Duties and Responsibilities: Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates highly advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of highly complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable highly advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes detailed technical documentation for highly complex EDA/IP/ASIC projects; reviews technical documentation for junior engineers. Level of Responsibility: Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.
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Qualcomm Atheros, Inc. Job Area:
Engineering Group, Engineering Group > ASICS Engineering General Summary: Working with the WiFi algorithm and systems team to design and test advanced WiFi functionalities such as OFDM and OFDMA modulators and demodulators, transmit beamforming, timing and synchronization, RF impairment correction, adaptive filters. Working with the algorithms/systems/modeling team to obtain a fixed-point/finite-precision C/C++ model that is realizable in optimized ASIC hardware. Converting the finite-precision models into ASIC hardware using SystemC/C++ for HLS (High-Level Synthesis) as the primary hardware description language that meet the area and power targets. Working with the verification engineers to develop unit-level and integrated-level test-benches. Debugging the designs in stand-alone and integrated with the system. Synthesis and gate-level timing tasks related to the designed module and assist with verification and timing of the entire chip. Design quality check such as lint, CDC and low power rule checks. RTL-level and gate-level vector-based power analysis. Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Preferred Qualifications: Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. 9+ years of ASIC design, verification, validation, integration, or related work experience. 3+ years of experience with architecture and design tools. 3+ years of experience with scripting tools and programming languages. 3+ years of experience with design verification methods. 2+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above). Principal Duties and Responsibilities: Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates highly advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of highly complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable highly advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes detailed technical documentation for highly complex EDA/IP/ASIC projects; reviews technical documentation for junior engineers. Level of Responsibility: Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.
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