Principal Analog Design Engineer

Principal Analog Design Engineer A leading premier chip and silicon IP provider, is seeking an exceptional Analog Design Engineer to join our Bufferchip Design team in Agoura Hills, California. You'll collaborate with some of the brightest inventors and engineers in the world to develop innovative products that enhance data speed and security. Position Overview: As an Analog Design Engineer, you will report to the Sr. Director of Engineering and will be responsible for the following: Key Responsibilities: Ownership of Designs: Take full ownership of analog designs at the chip and/or block level. Architecture Definition: Define optimal architectures to meet competitive product specifications. Circuit Design: Design, simulate, and characterize high-performance and high-speed circuits, including transmitters, receivers, ADCs, DACs, LDOs, PLLs, DLLs, and PI circuits. Model Creation: Develop high-level models for design tradeoff analysis and behavioral models for verification simulations. Floorplan Coordination: Create floorplans and collaborate with the layout team to ensure post-extraction performance meets specifications. Documentation: Document analysis and simulations to validate that designs achieve critical electrical and timing parameters as part of the pre-silicon verification flow. Testing Collaboration: Work with the Lab/System team on test plans, silicon bring-up, and characterization. Standards Dissemination: Understand and communicate applicable standards and their relevance to projects within the team. Mentorship: Mentor junior designers to foster skill development and knowledge sharing. Qualifications: Experience and in-depth knowledge of Advantest V93k required Education: MS in Electrical Engineering with 5+ years of experience or a PhD in Electrical Engineering with 2+ years of experience in CMOS analog circuit design. Positions may be tailored based on experience level. Circuit Experience: Prior experience in designing at least one of the following circuits: transmitter, receiver (including CTLE, DFE), PLL, DLL, PI, or clock distribution. Design Knowledge: Strong understanding of design principles and practical design tradeoffs. Fundamental Circuit Knowledge: Fundamental knowledge of basic building blocks such as bias circuits, op-amps, and LDOs. Memory Interfaces: Experience with memory interfaces like DDR4/5 or serial links such as PCIe is highly desirable. Process Experience: Prior design experience in FinFET processes and digitally-assisted design is a plus. Modeling Skills: Experience in modeling with MATLAB, Verilog-A, or Verilog is desirable. R&D Experience: Experience in leading R&D and future technology development projects is a plus. Communication Skills: Strong written and verbal communication skills, along with the ability to work effectively in cross-functional and globally dispersed teams. Salary Range: $130,400 to $223,000(DOE) Location: Agoura Hills, CA Type: Full-time Submit resumes to Jobs@OSIEngineering.com Diane Chen 408.550.2800 x130