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CV Library is hiring: Hardware Design Engineer 5 in Mountain View

CV Library, Mountain View, CA, United States, 94039

Job Title: Hardware Design Engineer 5

Location: Mountain View, CA

Duration: 8 months (Chance for Extension)

Summary:

We are looking for a Senior Silicon Validation Engineer to work in the dynamic Artificial Intelligence (AI) Silicon Engineering team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment.

Candidate will be responsible for Pre Silicon RTL Verification, Post Silicon Validation as well as Systems Level Testing. It involves driving system team enablement and product deployment in the data center at scale.

Qualifications

Required/Minimum Qualifications

  1. 10+ years of related technical engineering experience
  2. Hands-on experience with validation for multiple product cycles from definition to Silicon, including writing test plans, developing tests, debugging failures, and developing tools for pre-silicon and post-silicon environments.
  3. Solid programming skills in C/C++, System Verilog, Assembly, Python
  4. Good knowledge of advanced computer architecture and boot flow
  5. Experience with high-speed IOs and industry standard bus/parallel/serial protocols like Ethernet, PCIE, JTAG, AXI, AHB, and I2C
  6. Good communication skills, team player, self-driven and problem-solving ability

Other Requirements:

Ability to meet customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Cloud Background Check. This position will be required to pass the Cloud background check upon hire/transfer and every two years thereafter.

Responsibilities

The Silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering high-quality product that can perform complex and high-performance functions in an extremely efficient manner.

  1. Lead key components of functional validation of complex ASIC SOC and FPGA SOC
  2. Perform Pre-Silicon SoC verification and post-silicon/FPGA validation by defining testing strategies
  3. Work with cross-functional teams, Architecture, Design, Verification, and Partner teams for project execution and also influence next designs
  4. Develop Test plan, C tests, and infrastructure to complete functional validation of complex design and report bugs/issues
  5. Running tests, debugging failures, creating stress and performance scenarios to meet test plan goals
  6. Actively participate in chip bring up and write test firmware to support various teams
  7. Innovate to improve validation efficiency through methodologies and tools
  8. Coach and mentor others in your areas of expertise
  9. Demonstrate core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement

Nice to haves:

  1. Hardware Debugging
  2. FPGA Timing/Speed Optimization
  3. Synopsys HAPS System
  4. C/C++
  5. AXI Bus
  6. Microprocessor System

Top 3 Hard Skills Required + Years of Experience

  1. Minimum 10 YOE: Design Verification work
  2. Minimum 5 YOE: UVM, Testbench development and debugging
  3. Minimum 5 YOE: Test planning, Test writing and Scripting
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