Chip-Level Design Verification Engineer

Chip-Level Design Verification Engineer

5 openings, immediate start

12+ months assignment with possible extensions

Location: San Jose, San Diego or Irvine (onsite only)

Compensation: $80 - $100/hr 1099 or Corp-to-Corp

Eligibility: US Citizen or US Permanent Resident

Seeking an experienced Senior Design Verification Engineer with expertise in Chip Level Verification, HDMI, and SystemVerilog/UVM. The ideal candidate will lead verification efforts for complex digital circuits.

Requirements:

1. 5+ years of experience in design verification engineering
2. Chip-level verification expertise
3. Strong System Verilog and UVM skills
4. Experience with HDMI and PCIe (Gen5/Gen6) interfaces
5. Strong debugging and problem-solving skills
6. Excellent communication and teamwork skills
7. Prefer Chip Level but good IP experience like AXI, AMBA, I2C, UART, etc. is acceptable

#ChipLevel #DesignVerification #ChipLevelVerification #UVM #SystemVerilog