DRAM HBM Validation

Responsibilities: • Collaborate with design, verification, and integration engineers to define memory controller and PHY requirements. • Work with Memory Controller, DDRPHY/HBMPHY, and DRAM vendors to optimize main memory performance and power. • Validate SoC memory controller and PHY integration and help verification of features in simulation and emulation. • Oversee internal and external HBM silicon and package level testing. • Develop bring-up and debug methodologies for DDR and HBM interfaces. • Perform Post-Si validation. Qualifications: • Minimum 5 years of experience. Required Skills: • Knowledge of DRAM architectures and memory organization. • Experience with DRAM simulation and interface verification (HBM2E/HBM3 PHY, Memory Controller). • Understanding of memory test patterns and DRAM reliability. • Excellent hardware and software debugging skills. • Strong teamwork and interpersonal skills. • Understanding of computer architecture and micro-architecture. • Programming experience in C/C++/Python. Preferred Skills: • Master's or PhD Degree with 3 years of relevant industry experience. • Experience with HBM2E/3/3E/DDR5/LPDDR4 based products. • Bachelor’s degree with a minimum of 5 years relevant industry experience. • Experience with HBM2E/3/3E/DDR5/LPDDR4 based products.