ZipRecruiter
Senior Memory FW Engineer
ZipRecruiter, Boxborough, Massachusetts, us, 01719
We are looking for
Senior Memory FW Engineer
for our client in
Boxborough, MA . Job Title:
Senior Memory FW Engineer Job Location:
Boxborough, MA Job Type:
Contract Pay Range:
$65/hr - $70/hr Responsibilities: Firmware design and development of DDR PHY & DRAM Training steps. Firmware development of DDR PHY for ATE Testing, IP Char & SoC Power. Pre-silicon FW coding and simulation against Architectural and RTL models. Post-silicon lab bring-up and optimization of DDR Init and Run Time FW. Post-silicon DDR Training enhancements to enable robust links for higher reliability / higher frequency margin. Working with SoC/Product firmware teams to define features and specs. Preference And Skill Sets: +5 years’ experience as firmware engineer. Excellent knowledge of C, C++ and any scripting languages such as Python. Good knowledge of Verilog/SystemVerilog and digital simulation debugging. Ability to adapt and learn new toolsets and frameworks is required. Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware level clocking and synchronization is a plus. Post-silicon experience developing firmware on real hardware is required. Experience with SERDES, DDR, and Memory Controller Design is a plus. Strong understanding of computer organization/architecture. Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc. Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.). Education: Bachelor’s degree in electrical or computer engineering is strongly desired. A Master's or PhD degree is a plus.
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Senior Memory FW Engineer
for our client in
Boxborough, MA . Job Title:
Senior Memory FW Engineer Job Location:
Boxborough, MA Job Type:
Contract Pay Range:
$65/hr - $70/hr Responsibilities: Firmware design and development of DDR PHY & DRAM Training steps. Firmware development of DDR PHY for ATE Testing, IP Char & SoC Power. Pre-silicon FW coding and simulation against Architectural and RTL models. Post-silicon lab bring-up and optimization of DDR Init and Run Time FW. Post-silicon DDR Training enhancements to enable robust links for higher reliability / higher frequency margin. Working with SoC/Product firmware teams to define features and specs. Preference And Skill Sets: +5 years’ experience as firmware engineer. Excellent knowledge of C, C++ and any scripting languages such as Python. Good knowledge of Verilog/SystemVerilog and digital simulation debugging. Ability to adapt and learn new toolsets and frameworks is required. Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware level clocking and synchronization is a plus. Post-silicon experience developing firmware on real hardware is required. Experience with SERDES, DDR, and Memory Controller Design is a plus. Strong understanding of computer organization/architecture. Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc. Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.). Education: Bachelor’s degree in electrical or computer engineering is strongly desired. A Master's or PhD degree is a plus.
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