Design Verification Engineer

Design Verification Engineer – 6 Month Contract – Hybrid Onsite in San Jose (3/4 days a week in office) The Company We are currently recruiting for a well-known Electronics manufacturer, specifically for their research center which serves as a global hub for advanced innovation, driving breakthroughs in cutting-edge technology. With a strong presence worldwide, its teams focus on areas such as artificial intelligence, next-generation networks, robotics, IoT, and semiconductor development. Renowned for its collaborative environment, the center brings together world-class scientists and engineers to create transformative solutions that enhance user experiences across a diverse range of products The Role Join a dynamic team as a Design Verification Engineer, where you’ll play a crucial role in ensuring the functionality and reliability of GPU subsystems, including Shader, Texture, and Memory Systems. Your expertise will contribute to building robust, scalable verification environments and driving test coverage to closure. This is an opportunity to collaborate with architects and designers on cutting-edge GPU technologies. The roles responsibilities will involve Triage regression failures and implement testbench updates. Debug functional errors in RTL models using advanced simulation and debugging tools. Maintain efficient and clean regression processes. Develop scalable SystemVerilog/UVM testbenches for unit and/or cluster-level verification. Review architecture and micro-architecture specifications in detail. Collaborate closely with architects and RTL designers to align on functionality. Define, maintain, and execute comprehensive verification test plans. Generate and run test cases on logic simulation models. Develop functional coverage models and SystemVerilog assertions. Drive functional and code coverage to completion. Integrate C++ reference models into scoreboards for enhanced verification. Requirements: 5–15 years of experience in a design verification role. Proficiency in SystemVerilog, UVM/OVM, and object-oriented programming with C++. Knowledge of GPU architecture; experience with Shader, Texture, or Memory Systems is a plus. Expertise in coverage-driven verification methodologies, including functional and code coverage. Hands-on experience with SystemVerilog/UVM constraint-random testbench creation and debugging. Strong scripting skills in Python or Perl for automation and process efficiency. Solid understanding of micro-architecture, logic design, FSMs, and datapath pipelines. Proven track record in test planning, testbench architecture, and coverage/assertion development. Strong debugging, programming, and algorithm development skills. Excellent communication skills, both verbal and written.