Inspire Semiconductor, Inc.
Senior RTL Design Engineer
Inspire Semiconductor, Inc., Austin, Texas, us, 78716
InspireSemi is developing multi-thousand core RISC-V SoC’s for HPC & AI (High-Performance Computing), engineering/scientific, and graph analytics applications.
In this position, the successful candidate will be responsible for RTL design and verification of complex CPU and peripheral subsystems.
Job Responsibilities
Developing and documenting microarchitectures
Block- and system-level RTL coding in Verilog and SystemVerilog.
Synthesizing designs and providing timing constraints to the Physical Design team
Working with a verification team to define the test plan and thoroughly verifying a design
Qualifications
BS or higher degree in electrical or computer engineering
5+ years designing CPU cores, subsystems, and/or high-speed digital peripheral interfaces
Expert in RTL coding, IP integration, simulation, and synthesis
Strong verification, debugging, and PPA optimization skills
Preferred Experience
Cadence EDA toolchain, particularly Xcelium and Genus
Verification and quality checks (Lint, CDC, formal LEC)
Hardware/software codesign and software-driven verification
Familiarity with automated place and route/physical design (Innovus)
RISC-V CPU design, including floating-point and load/store subsystems
Low power and multi-power domain design
Programming (C/C++/assembly) and scripting (Perl, Python, Tcl)
Test pattern development and post-silicon debug
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In this position, the successful candidate will be responsible for RTL design and verification of complex CPU and peripheral subsystems.
Job Responsibilities
Developing and documenting microarchitectures
Block- and system-level RTL coding in Verilog and SystemVerilog.
Synthesizing designs and providing timing constraints to the Physical Design team
Working with a verification team to define the test plan and thoroughly verifying a design
Qualifications
BS or higher degree in electrical or computer engineering
5+ years designing CPU cores, subsystems, and/or high-speed digital peripheral interfaces
Expert in RTL coding, IP integration, simulation, and synthesis
Strong verification, debugging, and PPA optimization skills
Preferred Experience
Cadence EDA toolchain, particularly Xcelium and Genus
Verification and quality checks (Lint, CDC, formal LEC)
Hardware/software codesign and software-driven verification
Familiarity with automated place and route/physical design (Innovus)
RISC-V CPU design, including floating-point and load/store subsystems
Low power and multi-power domain design
Programming (C/C++/assembly) and scripting (Perl, Python, Tcl)
Test pattern development and post-silicon debug
#J-18808-Ljbffr