Analog Group
Sr. Digital Design Engineer
Analog Group, San Jose, California, United States, 95199
The Sr. Digital Design Engineer candidate must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Other key skills include technical/project leadership, documentation, RTL design knowledge, backend flow and tools knowledge. Candidate will be expected to lead designer, verification, and be technical focus on one or more device and/or sections. Candidate will also be expected to support pre/post-silicon design validation and support Design/ATE/Application & Systems group.
Company products include: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as broadband modems, notebooks, cell phones, telecom, fiber optics, digital camera, automobile and network equipment.
Job Function:
Digital Design (RTL design): ASIC or FPGA from concept to implementation. Digital Verification: Development test plans, test benches and automated test cases. Responsible for synthesis, timing closure, and formal verification. Create scripting to support design and verification automation. Estimate and manage time/tasks completion to target schedule. Qualifications:
3-5 years’ experience in design plus verification of ASIC or FPGA. Strong knowledge of ASIC development process and digital design techniques. Proficient in standard DV languages (Verilog, SystemVerilog, UVM) and automated regression testcase development, and reporting/tracking coverage metrics. Experience with:
Programming, scripting and automation languages (C/C++, shell, Perl, TCL, Python, etc.). Digital signal processing and filter design.
Experience with the following desired:
Audio or video applications.
Embedded designs and/or firmware development. Knowledge of power management industry/applications. I2C, SPI, USB, PMBUS. Education:
Requires MSEE/Ph.D. or equivalent. Reference Number: MMMP113 Job Features
Job Category
Digital, Digital Power, Firmware/Embedded, Power Management, Semiconductor
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Digital Design (RTL design): ASIC or FPGA from concept to implementation. Digital Verification: Development test plans, test benches and automated test cases. Responsible for synthesis, timing closure, and formal verification. Create scripting to support design and verification automation. Estimate and manage time/tasks completion to target schedule. Qualifications:
3-5 years’ experience in design plus verification of ASIC or FPGA. Strong knowledge of ASIC development process and digital design techniques. Proficient in standard DV languages (Verilog, SystemVerilog, UVM) and automated regression testcase development, and reporting/tracking coverage metrics. Experience with:
Programming, scripting and automation languages (C/C++, shell, Perl, TCL, Python, etc.). Digital signal processing and filter design.
Experience with the following desired:
Audio or video applications.
Embedded designs and/or firmware development. Knowledge of power management industry/applications. I2C, SPI, USB, PMBUS. Education:
Requires MSEE/Ph.D. or equivalent. Reference Number: MMMP113 Job Features
Job Category
Digital, Digital Power, Firmware/Embedded, Power Management, Semiconductor
#J-18808-Ljbffr