Rival
Fabric/Interconnect Architect
Rival, Santa Clara, California, us, 95053
Our mission is to create computing platforms (HW/SW co-design) that will transform the industry with the most advanced technologies. As fabric architect, you will be responsible for the internal interconnect architecture specification and its performance, power, area requirements. This will cover both coherent and non-coherent interconnects and chiplet-to-chiplet connections. You will be working with the Silicon team (eg. RTL/microarchitecture, DV, PD, Perf, DFT) members and industry consortiums such as UCIe.Requirements
Thorough knowledge of large scale on-chip fabric or on-chip interconnect architectureKnowledge of on-chip network protocols: AMBA, AXI, CHI, ACE, Tilelink or APB.Knowledge of cache coherent memory systems and interconnect.Familiarity with different on-chip network topologies (ring, mesh, xbar etc).Knowledge of SystemVerilog or Verilog, C or C++, scripting languages such as PythonExperience with functional and performance simulatorsKnowledge of logic design principles along with timing and power implicationsUnderstanding of low power architecture techniquesUnderstanding of high performance techniques and trade-offs in fabric architectureResponsibilities
Architecture development and specification - from early high-level architectural exploration through micro architectural direction and writing a detailed specificationCoherent and non-coherent interconnects within the chip, coherency protocol, directory structure, bandwidth and latency targetsDevelopment, assessment, and refinement of Architecture to target power, performance, area, and timing goalsHelping produce and review validation plans for functionality and performanceEducation and experience
PhD, Master’s Degree or Bachelor’s Degree in technical subject area.This is an architecture lead position so a senior level of experience is expected.
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Thorough knowledge of large scale on-chip fabric or on-chip interconnect architectureKnowledge of on-chip network protocols: AMBA, AXI, CHI, ACE, Tilelink or APB.Knowledge of cache coherent memory systems and interconnect.Familiarity with different on-chip network topologies (ring, mesh, xbar etc).Knowledge of SystemVerilog or Verilog, C or C++, scripting languages such as PythonExperience with functional and performance simulatorsKnowledge of logic design principles along with timing and power implicationsUnderstanding of low power architecture techniquesUnderstanding of high performance techniques and trade-offs in fabric architectureResponsibilities
Architecture development and specification - from early high-level architectural exploration through micro architectural direction and writing a detailed specificationCoherent and non-coherent interconnects within the chip, coherency protocol, directory structure, bandwidth and latency targetsDevelopment, assessment, and refinement of Architecture to target power, performance, area, and timing goalsHelping produce and review validation plans for functionality and performanceEducation and experience
PhD, Master’s Degree or Bachelor’s Degree in technical subject area.This is an architecture lead position so a senior level of experience is expected.
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