Rival
Coherent Interconnect Microarchitecture & Logic Design - Full Time
Rival, Portland, Oregon, United States, 97204
Rivos is on a mission to build the best RISC-V enterprise systems in the world with class leading performance, power, security and RAS features. We are seeking Interconnect/Fabric Design experts to join our team in building the best RISC-V compute systems in the world.Responsibilities
Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specificationDevelopment, assessment, and refinement of RTL design to target power, performance, area, and timing goalsValidation - support test bench development and simulation for functional and performance verificationPerformance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performanceDesign delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and powerRequirements
Thorough knowledge of large scale on-chip coherent or non-coherent interconnect/fabric architectureKnowledge of one or more on-chip network protocols: AMBA, AXI, CHI, ACE, Tilelink, APB or similar protocolsKnowledge of cache coherent memory systems and interconnectKnowledge of system caches and directory snoop filter protocolsFamiliarity with different on-chip network topologies: mesh, ring, crossbar, etcUnderstanding of high performance and low power microarchitecture techniques and trade-offsProficiency in SystemVerilog or Verilog RTL codingKnowledge of logic design principles along with timing and power implicationsExperience with simulators and waveform debugging toolsEducation and Experience
PhD, Master’s Degree or Bachelor’s Degree in technical subject area.
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Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specificationDevelopment, assessment, and refinement of RTL design to target power, performance, area, and timing goalsValidation - support test bench development and simulation for functional and performance verificationPerformance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performanceDesign delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and powerRequirements
Thorough knowledge of large scale on-chip coherent or non-coherent interconnect/fabric architectureKnowledge of one or more on-chip network protocols: AMBA, AXI, CHI, ACE, Tilelink, APB or similar protocolsKnowledge of cache coherent memory systems and interconnectKnowledge of system caches and directory snoop filter protocolsFamiliarity with different on-chip network topologies: mesh, ring, crossbar, etcUnderstanding of high performance and low power microarchitecture techniques and trade-offsProficiency in SystemVerilog or Verilog RTL codingKnowledge of logic design principles along with timing and power implicationsExperience with simulators and waveform debugging toolsEducation and Experience
PhD, Master’s Degree or Bachelor’s Degree in technical subject area.
#J-18808-Ljbffr