Rival
Memory Controller Microarchitecture & Logic Design - Full Time
Rival, Fort Collins, Colorado, us, 80523
Rivos is on a mission to build the best enterprise SOCs in the world with class leading performance, power, security and RAS features. We are seeking Memory Controller and Logic Design experts to join our team in building the best high performance memory interface in the world.Responsibilities
Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specificationDevelopment, assessment, and refinement of RTL design to target power, performance, area, and timing goalsValidation - support test bench development and simulation for functional and performance verificationPerformance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performanceDesign delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and powerRequirements
Thorough knowledge of memory controller or PHY design and experience in one or more of the following memory technologies: DDR, LPDDR, HBMKnowledge of SystemVerilogExperience with simulators and waveform debugging toolsKnowledge of logic design principles along with timing and power implicationsUnderstanding of low power microarchitecture techniquesUnderstanding of high performance techniques and trade-offs in memory controller microarchitectureExperience using an interpretive language such as Perl or PythonEducation and Experience
PhD, Master’s Degree, or Bachelor’s Degree in technical subject area
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Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specificationDevelopment, assessment, and refinement of RTL design to target power, performance, area, and timing goalsValidation - support test bench development and simulation for functional and performance verificationPerformance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performanceDesign delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and powerRequirements
Thorough knowledge of memory controller or PHY design and experience in one or more of the following memory technologies: DDR, LPDDR, HBMKnowledge of SystemVerilogExperience with simulators and waveform debugging toolsKnowledge of logic design principles along with timing and power implicationsUnderstanding of low power microarchitecture techniquesUnderstanding of high performance techniques and trade-offs in memory controller microarchitectureExperience using an interpretive language such as Perl or PythonEducation and Experience
PhD, Master’s Degree, or Bachelor’s Degree in technical subject area
#J-18808-Ljbffr