SOC DESIGN VERIFICATION ENGINEER

Esperanto delivers high-performance, energy-efficient, and innovative computing solutions that are the compelling choice for the most demanding AI and non-AI applications. The changing, computationally intensive workloads of the machine learning era mandate a new clean-sheet solution, without the baggage of existing legacy architectures, or the programmability limitations of overspecialized hardware. Esperanto leverages the simple, elegant, open standard RISC-V ISA along with leading-edge system architectures to deliver flexibility, scalability, performance, and energy-efficiency advantages.ResponsibilitiesCreate verification content including testplans, test bench components, directed and constrained random tests, and functional coverageExecute testplans to fully verify SoC component blocksBroader responsibilities may include supporting full-chip simulation, emulation, and post-silicon bring upQualificationsAbility to clearly communicate across teams with multidisciplinary backgrounds5+ years of experience in CPU, IP or SoC verificationKnowledge of high-level verification flow methodology (testplan development, constrained random test generation and debug, coverage analysis and closure)Experience with a class-based testbench using System Verilog is requiredKnowledge of processors, cache, and cache coherence is requiredExperience with UVM/OVM is requiredBS/MS EENice to HaveExperience with Tcl is a plusExperience with C and RISC-V assembly programming is a plusExperience with Python, Perl, or other scripting languages is a plus

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