Eliyan
Digital Design Engineer
Eliyan, San Francisco, California, United States, 94199
Digital Design EngineerJoin the leading chiplet startup! As an Eliyan Digital Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will be defining, implementing, and ensuring correctness of novel RTL for major blocks. You will work with a cross-functional team of industry experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.Key Responsibilities
Define microarchitecture and design of major blocksAuthor microarchitecture document and review with key staffWrite RTL that meets specsWork with Verification team to root cause and fix bugsWork with the physical design team to ensure best-in-class PPAWork with the verification team to create and review assertions and checkers, stimulus, and coverage metricsMinimum Qualifications
Expertise in general logic design, and best-in-class RTL codingKnowledge of memory systems (DDR, LPDDR, GDDR, HBM) a plusKnowledge of PCI, CXL, and on-chip interconnect (NoC, AXI) a plusGeneral knowledge of RTL simulation tools and related scripting languagesBS EE or equivalent, with 5 years of experienceIdeal Qualifications
Deep expertise in memory system and memory controller designKnowledge of UPF and power-aware designsExperience working with Analog/Mixed-Signal circuits and DRAM PHYsExperience with Verilog real number modeling (RNM) or Verilog AMS modelingMS/PhD EE or equivalent, with 7 years of experience
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Define microarchitecture and design of major blocksAuthor microarchitecture document and review with key staffWrite RTL that meets specsWork with Verification team to root cause and fix bugsWork with the physical design team to ensure best-in-class PPAWork with the verification team to create and review assertions and checkers, stimulus, and coverage metricsMinimum Qualifications
Expertise in general logic design, and best-in-class RTL codingKnowledge of memory systems (DDR, LPDDR, GDDR, HBM) a plusKnowledge of PCI, CXL, and on-chip interconnect (NoC, AXI) a plusGeneral knowledge of RTL simulation tools and related scripting languagesBS EE or equivalent, with 5 years of experienceIdeal Qualifications
Deep expertise in memory system and memory controller designKnowledge of UPF and power-aware designsExperience working with Analog/Mixed-Signal circuits and DRAM PHYsExperience with Verilog real number modeling (RNM) or Verilog AMS modelingMS/PhD EE or equivalent, with 7 years of experience
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