Samsung Electronics Perú
DTCO and PPA Engineer
Samsung Electronics Perú, San Diego, California, United States, 92189
Position Summary
Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
Role and Responsibilities
You will join our growing Global Advanced Technology Enablement team that is specialized in driving technology development across Samsung System LSI business. We engage with Foundry partners from the very early phase to thoroughly explore target technology for next-generation SoC products.
You will collaborate on DTCO activity from early TD up to tape-out and revision.
You are passionate about driving Foundation IP (FIP) Architecture exploration for new technology. This includes coordinating with the global FIP design team (both in-house and Foundry).
You are a domain expert in one or more technical areas, such as Advanced Methodology development, ranging from Physical Design (P&R), transistor-level/circuit Layout, Signoff, Electrical/Physical Verification up to DFM. You will help our team coordinate with global design methodology teams and will often directly drive global R&D teams from various EDA vendors.
You are an innovator. You thrive on driving future-oriented changes and generating creative perspectives and solutions. You bring fresh ideas to challenge past practices, approaches, and old ways of thinking to introduce new innovation opportunities.
You are skilled at driving cross-company collaboration with a global perspective by creating synergetic ways of working using effective communications and proactive partnership.
Skills and Qualifications
6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a PhD.
Technology Enablement (TE) and DTCO experience at advanced technology nodes (below 5nm). The activity includes technology, logic and memory cell architecture exploration. Multiple-Foundry experience is a plus.
Foundation IP (both Library Cell and SRAM Memory) design experience up to MTO and post-Silicon activity.
Experienced in Physical Design (e.g., Synthesis and P&R), PDN design, library exploration, EDA tools, etc. EDA interfacing experience is a plus.
Total Rewards
At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $144,345 and $257,336. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.
Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.
This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.
Trade Secrets
By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.
#SARC #ACL #Hybrid
#J-18808-Ljbffr
Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
Role and Responsibilities
You will join our growing Global Advanced Technology Enablement team that is specialized in driving technology development across Samsung System LSI business. We engage with Foundry partners from the very early phase to thoroughly explore target technology for next-generation SoC products.
You will collaborate on DTCO activity from early TD up to tape-out and revision.
You are passionate about driving Foundation IP (FIP) Architecture exploration for new technology. This includes coordinating with the global FIP design team (both in-house and Foundry).
You are a domain expert in one or more technical areas, such as Advanced Methodology development, ranging from Physical Design (P&R), transistor-level/circuit Layout, Signoff, Electrical/Physical Verification up to DFM. You will help our team coordinate with global design methodology teams and will often directly drive global R&D teams from various EDA vendors.
You are an innovator. You thrive on driving future-oriented changes and generating creative perspectives and solutions. You bring fresh ideas to challenge past practices, approaches, and old ways of thinking to introduce new innovation opportunities.
You are skilled at driving cross-company collaboration with a global perspective by creating synergetic ways of working using effective communications and proactive partnership.
Skills and Qualifications
6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a PhD.
Technology Enablement (TE) and DTCO experience at advanced technology nodes (below 5nm). The activity includes technology, logic and memory cell architecture exploration. Multiple-Foundry experience is a plus.
Foundation IP (both Library Cell and SRAM Memory) design experience up to MTO and post-Silicon activity.
Experienced in Physical Design (e.g., Synthesis and P&R), PDN design, library exploration, EDA tools, etc. EDA interfacing experience is a plus.
Total Rewards
At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $144,345 and $257,336. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.
Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.
This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.
Trade Secrets
By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.
#SARC #ACL #Hybrid
#J-18808-Ljbffr